DS730 Datasheet, PDF (39/46 Pages) Xilinx, Inc – LogiCORE IP Video Direct

LogiCORE IP Video Direct Memory Access v1.1
XSVI Data Interface
When the "Bus Interface" is set to XSVI, the VDMA FIFO data interface is replaced with the XSVI streaming data
interface. The XSVI interface makes it easier to connect the Video DMA to IP cores that stream video data. When
using the XSVI interface on the Video DMA, the user is responsible for guaranteeing that the logic that is connected
to the VDMA's XSVI bus does not overflow or underflow the FIFOs of the VFBC. The vdma_wd_full,
vdma_wd_almost_full, vdma_rd_empty and vdma_almost_empty signals are provided on the core even
when the XSVI bus mode is selected. The VDMA command interfaces are also removed when the XSVI bus is
selected. As a result, the Video DMA can only be used in Register Command Mode.
The write side of the XSVI bus consists of 4 input signals: xsvi_wd_clk_in, xsvi_wd_vsync_in,
xsvi_wd_write_in and xsvi_wd_data_in. The xsvi_wd_clk_in is used to drive the write side of the
VDMA. The xsvi_wd_vsync_in is use as the frame sync if the "Use Frame Sync" option is selected. The
xsvi_wd_active_video_in is used to specify when valid data should be written. The xsvi_wd_data_in is
the write side data bus.
The read side of the XSVI bus is more complicated because data is being read from a FIFO onto the streaming video
bus. The user is responsible for generating the necessary streaming video control signals to properly frame the data.
The VDMA provides inputs for each of the video control signals and outputs the signals on the corresponding
video control output signal after a one cycle delay. The xsvi_rd_clk_in signal is used to drive the read side of the
VDMA. The xsvi_rd_vsync is used for the frame sync if the "Use Frame Sync" option is selected. The
xsvi_rd_active_video_in is used to read data from the VFBC FIFO. The xsvi_rd_data_out is the read side
data bus.
Figure 14 illustrates read and write operations using the XSVI bus on a Video DMA in Read/Write mode. The Video
DMA is operating in Register Command Mode with "Use Frame Sync" enabled. In this case the read and write
frame sync signals arrive at the same time. The Video DMA sends a write command to the VFBC and commences
with the write operation. Next the Video DMA sends a read command to the VFBC. Once the VFBC reports back
that the read FIFO has data available, the Video DMA begins the read transfer. Note that the XSVI read control
signals on the output side are delayed by one clock cycle in order to match up with the one cycle delay to read data
from the VFBC read FIFO.
X-Ref Target - Figure 14
Figure 14: Video DMA XSVI Data Interface, Read and Write Commands
DS730 September 21, 2010
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Product Specification