DS730 Datasheet, PDF (14/46 Pages) Xilinx, Inc – LogiCORE IP Video Direct

LogiCORE IP Video Direct Memory Access v1.1
Table 1: Video DMA pCore Memory Mapped Register Set (Cont’d)
Address (hex)
Register Name
Access Type
Description
BASEADDR +
0x008c
Control Read
Start Address 7
R/W
Start Address of Read Frame Store 7
BASEADDR +
0x0090
Control Read
Start Address 8
R/W
Start Address of Read Frame Store 8
BASEADDR +
0x0094
Control Read
Start Address 9
R/W
Start Address of Read Frame Store 9
BASEADDR +
0x0098
Control Read
Start Address 10
R/W
Start Address of Read Frame Store 10
BASEADDR +
0x009c
Control Read
Start Address 11
R/W
Start Address of Read Frame Store 11
BASEADDR +
0x00a0
Control Read
Start Address 12
R/W
Start Address of Read Frame Store 12
BASEADDR +
0x00a4
Control Read
Start Address 13
R/W
Start Address of Read Frame Store 13
BASEADDR +
0x00a8
Control Read
Start Address 14
R/W
Start Address of Read Frame Store 14
BASEADDR +
0x00ac
Control Read
Start Address 15
R/W
Start Address of Read Frame Store 15
BASEADDR +
0x0F0
Version Register
R
Reports Version of the Video DMA core
28:31 Major Version Number. Set to 0x2.
20:27
Minor Version Number. Set to
0x01.
16:19 Revision Number. Set to 0xA.
0:15 Reserved
BASEADDR + _{Global Interrupt Enable}
0x021c
R/W
Global Interrupt Enable
Writing a 1 to this bit will enable all
interrupts.
31:
Set to 0 (all interrupts disabled) by
default.
0:30 Reserved
BASEADDR +
0x0220
Interrupt Status/Clear
R/W
Interrupt Status when read, Interrupt Clear when
written
19:31 Reserved
18
Write FIFO Error
17
Write Cmd FIFO Error
Write Frame Count Interrupt
16
Indicates that the Frame count has
reached the frame count threshold.
Write 1 to clear.
Write Delay Count Interrupt
15
Indicates that the delay timeout
event has occurred. Write 1 to
clear.
DS730 September 21, 2010
www.xilinx.com
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Product Specification