DS730 Datasheet, PDF (10/46 Pages) Xilinx, Inc – LogiCORE IP Video Direct

LogiCORE IP Video Direct Memory Access v1.1
Table 1: Video DMA pCore Memory Mapped Register Set (Cont’d)
Address (hex)
Register Name
Access Type
Description
BASEADDR +
0x000c
Control Counters
R/W
Frame and Delay Counters
24:31
Read Frame Count
Send interrupt after this number of
frames has been read.
16:23
Read Delay Timer Count
Send interrupt after this number of
delay counter ticks for the read
DMA. The delay counter period is
controlled by a clock divider.
Write Frame Count
8:15 _{Send interrupt after this number of}
frames has been written.
Write Delay Timer Count
Send interrupt after this number of
0:7
delay counter ticks for the write
DMA. The delay counter period is
controlled by a clock divider.
BASEADDR +
0x0010
Status Counters
R
Frame and Delay Counters Status
24:31
Read Frame Counter Value
Indicates the number of frames left
to be read of the number specified
Read Frame Count.
16:23
Read Delay Count Value
Indicates the number of counter
ticks left of the number specified in
Read Delay Timer Count.
Write Frame Counter Value
8:15
Indicates the number of frames left
to be written of the number
specified in Write Frame Count.
Write Delay Count Value
0:7
Indicates the number of counter
ticks left of the number specified in
Write Delay Timer Count.
DS730 September 21, 2010
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Product Specification