DS730 Datasheet, PDF(18/46 Page) Xilinx, Inc

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DS730 Datasheet, PDF (18/46 Pages) Xilinx, Inc – LogiCORE IP Video Direct

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LogiCORE IP Video Direct Memory Access v1.1

pCore I/O Signals

The I/O signals for the Video DMA pCore are shown in Table 3. The signals can be broken into three groups:

Streaming Video, pCore Gen-Lock and PLB v4.6 signals. The Streaming Video Signals are specified in Table 4. The

pCore Gen-Lock signals are specified in Table 5. The PLB v4.6 signals are specified in Table 6.

The selected modes of the Video VDMA pCore determine the signals that are available to the user. When the

Bus_Interface is set to VDMA, the VDMA bus interface is available and the XSVI bus interface is not. Conversely,

when the XSVI is selected the XSVI bus interface is available and the VDMA bus interface is not. When the

DMA_Mode is set to Read/Write, both read and write related signals are available. When Read_Only mode is

selected, only read related signals are available. When Write_Only mode is selected, only write related signals are

available.

Table 3: Video DMA pCore I/O Diagram

VFBC Command Interface

VFBC_cmd_full

VFBC_cmd_almost_full

VFBC_cmd_idle

VFBC_cmd_clk

VFBC_cmd_reset

VFBC_cmd_data

VFBC_cmd_write

VFBC_cmd_end

VFBC Read Interface

VFBC_rd_empty

VFBC_rd_almost_empty

VFBC_rd_data

VFBC_rd_clk

VFBC_rd_reset

VFBC_rd_read

VFBC_rd_end_burst

VFBC_rd_flush

VFBC Write Interface

VFBC_wd_full

VFBC_wd_almost_full

VFBC_wd_clk

VFBC_wd_reset

VFBC_wd_write

VFBC_wd_end_burst

VFBC_wd_flush

VFBC_wd_data

VFBC_wd_be

VDMA Read Command Interface

VDMA_rcmd_full

VDMA_rcmd_almost_full

VDMA_rcmd_idle

VDMA_rcmd_clk

VDMA_rcmd_reset

VDMA_rcmd_data

VDMA_rcmd_write

VDMA_rcmd_end

VDMA Read Interface