DS730 Datasheet, PDF (37/46 Pages) Xilinx, Inc – LogiCORE IP Video Direct

LogiCORE IP Video Direct Memory Access v1.1
Master Mode
When the Video DMA is used in Gen-Lock Master mode, the core operates as normal. The Grey coded Start
Address Register index that the slave should use is out on the frame_ptr_out bus. The bus name depends upon
the processor interface and read/write mode being used. For the pCore interface, the m_wd_frame_ptr_out or
m_rd_frame_ptr_out is used. For the GPP interface, the wd_frame_ptr_out or rd_frame_ptr_out is used.
Slave Mode
When the Video DMA is used as a Gen-Lock Slave, it uses the Grey coded Start Address Register index specified by
the Gen-Lock Master to determine which Start Address Register should be used for the next VFBC command. The
Video DMA can be configured to handle multiple Gen-Lock Masters, although it can follow only one Master at any
one time. The number of Gen-Lock Masters is specified by the “Write Number of Masters” or the “Read Number of
Masters” parameters in the CORE Generator GUI depending upon whether the core is used in “Write Only” or
“Read Only” mode respectively. The number of masters can be set between 1 and 16. When using the pCore
interface, the number of masters should be limited to the range of 1 – 8.
The “Read Pointer Number” and “Write Pointer Number” registers are used to specify which of the masters is in
control. The registers use indexes of 0 – 15. When using the pCore interface, the s_wd_frame_prt_in(1-8) and
s_rd_frame_ptr_in(1-8) buses are used to interface with the Gen-Lock masters. When using the GPP interface,
the wd_frame_prt_in and rd_frame_ptr_in buses are used. For the GPP interface, all of the masters are
concatenated together into a single bus. The master at the lowest portion of the bus corresponds with index 0, and
so on.
Fsync Synchronization
In many video applications, it is advantageous to control when the Video DMA begins each data transfer. This
synchronization can be achieved by using a system timing signal that is connected to the fsync pin on the core. The
fsync signal can be derived from various sources depending upon what is available in the system. Most commonly
the fsync is driven by a Video Timing Controller or by the vsync or vblank signal associated with a streaming
video bus. When connecting the fsync signal to the vblank signal of a streaming video bus, be sure the vblank
is active high polarity as the VDMA will internally strobe the rising edge of the fsync input signal. It is
recommended to use the vsync signal if it is available to avoid resetting the internal logic of the VDMA during
active video lines.
When “Use Frame Sync” parameter is selected in the CORE Generator GUI, the Video DMA waits until it sees the
falling edge of the fsync signal before beginning a data transfer. Figure 11 shows an example of a write transfer
that has been synchronized to the fsync signal. Read transfers follow the same format. The fsync signal should
pulse only once per frame. Transitions while the Video DMA is processing a transfer could cause unpredictable
behavior.
X-Ref Target - Figure 11
Figure 11: Write Register Command Mode Synchronized to Fsync
DS730 September 21, 2010
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Product Specification