DS730 Datasheet, PDF (44/46 Pages) Xilinx, Inc – LogiCORE IP Video Direct

LogiCORE IP Video Direct Memory Access v1.1
Table 15: Virtex-6 Resource Estimates
Feature
Read_Only or Write_Only Mode
Core (1 Frame Store)
Each Additional Frame Store (GPP)
Each Additional Frame Store (pCore)
Non-Aligned Transfers
pCore Interface
Read/Write
Core (Read/Write, 1 Frame Store)
Each Additional Frame Store (GPP)
Each Additional Frame Store
Non-Aligned Transfers
(pCore) pCore Interface
LUTs
FFs
213
201
13
4
42
88
213
147
625
976
330
282
29
4
95
140
246
200
625
976
Performance
The following are typical clock frequencies for the target families. The maximum achievable clock may vary and can
depend on the size of the device, various aspects of the system design and other variables.
• Spartan-3A DSP: 150 MHz
• Spartan-6: 150 MHz
• Virtex-5: 225 MHz
• Virtex-6: 225 MHz
The Video DMA does not limit the throughput of the VFBC. When using the “Allow Non-Aligned Transfers”
option, delays may be added to the front and end of each transfer. The amount of delay is dependent upon the
selected data width. The maximum total delay for each valid data width is:
• 8- Bit: 127 cycles
• 16-Bit: 63 cycles
• 32-Bit: 7 cycles
• 64-Bit: 3 cycles
References
1. Processor Local Bus (PLB) v4.6
2. MPMC Data Sheet (VFBC PIM)
3. Video Timing Controller Data Sheet
DS730 September 21, 2010
www.xilinx.com
44
Product Specification