UG534 Datasheet, PDF (76/96 Pages) –

Chapter 1: ML605 Evaluation Board
Configuration Options
The FPGA on the ML605 Evaluation Board can be configured by the following methods:
• 3. 128 Mb Platform Flash XL, page 22
• 4. 32 MB Linear BPI Flash, page 22
• 5. System ACE CF and CompactFlash Connector, page 26
• 6. USB JTAG, page 28
For more information, see the Virtex-6 FPGA Configuration User Guide at
http://www.xilinx.com/support/documentation/user_guides/ug360.pdf.
Table 1-33: Mode Switch S2 Settings
Mode Pins (M2,M1,M0)
Configuration Mode
110
Slave SelectMAP
010
BPI Mode
101
JTAG
With the mode set to JTAG 101, the ML605 will not attempt to boot or load a bitstream from
either of the Flash devices. If a CompactFlash (CF) card is installed in the CF socket U73,
System ACE CF will attempt to load a bitstream from the CF card image address pointed to
by the image select switch S1. With no CF card present, the ML605 can be configured via
the onboard JTAG controller and USB download cable as described above.
With the mode set to either Slave SelectMAP 110, or BPI Mode 010, the FPGA will attempt
to configure itself from the selected Flash device as described in 3. 128 Mb Platform Flash
XL, page 22.
Note: S1 switch 4 is the System ACE controller enable switch. When ON, this switch allows the
System ACE to boot at power-on if it finds a CF card present. In order to boot from BPI Flash U4 or
Xilinx Platform Flash (U27) without System ACE contention, S1 switch 4 must be OFF.
76
www.xilinx.com
ML605 Hardware User Guide
UG534 (v1.8) October 2, 2012