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UG534 Datasheet, PDF (44/96 Pages) – | |||
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Chapter 1: ML605 Evaluation Board
15. IIC Bus
The ML605 implements four IIC bus interfaces at the FPGA.
The "MAIN" IIC bus hosts four items:
⢠FPGA U1 Bank 34 "MAIN" IIC interface
⢠8Kb NV Memory U6
⢠FMC HPC connector J64
⢠DDR3 SODIMM Socket J1
The "DVI" IIC bus hosts two items:
⢠FPGA U1 Bank 34 "DVI" IIC interface
⢠DVI codec U38 and DVI connector J63
The "LPC" IIC bus hosts two items:
⢠FPGA U1 Bank 33 "LPC" IIC interface
⢠FMC LPC connector J63
The "SFP" IIC bus hosts two items:
⢠FPGA U1 Bank 13 "SFP" IIC interface
⢠SFP module connector P4
The ML605 IIC bus topology is shown in Figure 1-14.
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ML605 Hardware User Guide
UG534 (v1.8) October 2, 2012
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