UG534 Datasheet, PDF (35/96 Pages) –

Detailed Description
Table 1-8 shows the PCIe connector (P1) that provides up to 8-lane access through the GTX
transceivers to the Virtex-6 FPGA integrated Endpoint block for PCIe designs.
Table 1-8: PCIe Edge Connector Connections
U1 FPGA
Pin
Schematic Net Name
P1 PCIe Edge Connector
Pin Number Pin Name
Description
Package
Placement
F1
PCIE_TXO_P
F2
PCIE_TXO_N
A16
A17
PERp0
PERn0
Integrated Endpoint block
transmit pair
GTXE1_X0Y15
H1
PCIE_TX1_P
H2
PCIE_TX1_N
A21
A22
PERp1
PERn1
Integrated Endpoint block
transmit pair
GTXE1_X0Y14
K1
PCIE_TX2_P
K2
PCIE_TX2_N
A25
A26
PERp2
PERn2
Integrated Endpoint block
transmit pair
GTXE1_X0Y13
M1
PCIE_TX3_P
M2
PCIE_TX3_N
A29
A30
PERp3
PERn3
Integrated Endpoint block
transmit pair
GTXE1_X0Y12
P1
PCIE_TX4_P
P2
PCIE_TX4_N
A35
A36
PERp4
PERn4
Integrated Endpoint block
transmit pair
GTXE1_X0Y11
T1
PCIE_TX5_P
T2
PCIE_TX5_N
A39
A40
PERp5
PERn5
Integrated Endpoint block
transmit pair
GTXE1_X0Y10
V1
PCIE_TX6_P
V2
PCIE_TX6_N
A43
A44
PERp6
PERn6
Integrated Endpoint block
transmit pair
GTXE1_X0Y9
Y1
PCIE_TX7_P
Y2
PCIE_TX7_N
A47
A48
PERp7
PERn7
Integrated Endpoint block
transmit pair
GTXE1_X0Y8
J3
PCIE_RXO_P
J4
PCIE_RXO_N
B14
B15
PETp0
PETn0
Integrated Endpoint block
receive pair
GTXE1_X0Y15
K5
PCIE_RX1_P
K6
PCIE_RX1_N
B19
B20
PETp1
PETn1
Integrated Endpoint block
receive pair
GTXE1_X0Y14
L3
PCIE_RX2_P
L4
PCIE_RX2_N
B23
B24
PETp2
PETn2
Integrated Endpoint block
receive pair
GTXE1_X0Y13
N3
PCIE_RX3_P
N4
PCIE_RX3_N
B27
B28
PETp3
PETn3
Integrated Endpoint block
receive pair
GTXE1_X0Y12
R3
PCIE_RX4_P
R4
PCIE_RX4_N
B33
B34
PETp4
PETn4
Integrated Endpoint block
receive pair
GTXE1_X0Y11
U3
PCIE_RX5_P
U4
PCIE_RX5_N
B37
B38
PETp5
PETn5
Integrated Endpoint block
receive pair
GTXE1_X0Y10
W3
PCIE_RX6_P
W4
PCIE_RX6_N
B41
B42
PETp6
PETn6
Integrated Endpoint block
receive pair
GTXE1_X0Y9
ML605 Hardware User Guide
www.xilinx.com
35
UG534 (v1.8) October 2, 2012