UG534 Datasheet, PDF (39/96 Pages) –

Detailed Description
X-Ref Target - Figure 1-13
Table 1-12: Board Connections for PHY Configuration Pins (Cont’d)
Pin
Connection on
Bit[2]
Bit[1]
Bit[0]
Board Definition and Value Definition and Value Definition and Value
CFG5
V_CC 2.5V
CFG6 PHY_LED_RX
DIS_FC = 1
SEL_BDT = 0
DIS_SLEEP = 1
INT_POL = 1
HWCFG_MD[3] = 1
75/50Ω= 0
SGMII GTX Transceiver Clock Generation
An Integrated Circuit Systems ICS844021I chip generates a high-quality, low-jitter, 125-
MHz LVDS clock from an inexpensive 25-MHz crystal oscillator. This clock is sent to the
GTX driving the SGMII interface. Series AC coupling capacitors are also present to allow
the clock input of the FPGA to set the common mode voltage.
X3
1 _R132
DNP
1%
2 _1/16W
25.000MHZ
VDDA_SGMIICLK
ICS84402II
1 _VDDA
2 _GND
SGMIICLK_XTAL_OUT
3 _{XTAL_OUT}
SGMIICLK_XTAL_IN
4 _{XTAL_IN}
U82
VDD_SGMIICLK
VDD ⁸
Q0 ⁷
NQ0 ⁶
OE ⁵
SGMIICLK_QO_C_P
SGMIICLK_QO_C_N
GND_SGMIICLK 125.00 MHz Clock
SGMIICLK_QO_P
SGMIICLK_QO_N
UG534_13_111709
Figure 1-13: Ethernet SGMII Clock - 125 MHz
Table 1-13 shows the connections and pin numbers for the PHY.
Table 1-13: Ethernet PHYConnections
U1 FPGA Pin Schematic Net Name
U80 M88E1111
Pin Number
Pin Name
AN14
PHY_MDIO
33
MDIO
AP14
PHY_MDC
35
MDC
AH14
PHY_INT
32
INT_B
AH13
PHY_RESET
36
RESET_B
AL13
PHY_CRS
115
CRS
AK13
PHY_COL
114
COL
AP11
PHY_RXCLK
7
RXCLK
AG12
PHY_RXER
8
RXER
AM13
PHY_RXCTL_RXDV
4
RXDV
AN13
PHY_RXD0
3
RXD0
AF14
PHY_RXD1
128
RXD1
AE14
PHY_RXD2
126
RXD2
AN12
PHY_RXD3
125
RXD3
ML605 Hardware User Guide
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UG534 (v1.8) October 2, 2012