UG534 Datasheet, PDF (33/96 Pages) –

Detailed Description
8. Multi-Gigabit Transceivers (GTX MGTs)
The ML605 provides access to 20 MGTs.
• Eight (8) of the MGTs are wired to the PCIe x8 Endpoint (P1) edge connector fingers
• Eight (8) of the MGTs are wired to the FMC HPC connector (J64)
• One (1) MGT is wired to SMA connectors (J26, J27)
• One (1) MGTs is wired to the FMC LPC connector (J63)
• One (1) MGT is wired to the SFP Module connector (P4)
• One (1) MGT is used for an SGMII connection to the Ethernet PHY (U80)
X-Ref Target - Figure 1-10
Note: xxx MHz = user specified frequency
SGMII 125 MHz LVDS
SMA xxx MHz LVDS
GTX_X0Y19
GTX_X0Y18
REFCLK0
REFCLK1
GTX_X0Y17
GTX_X0Y16
SGMII
SMA
SFP
FMC#2
100 MHz in from
PCIe Fingers
(HCSL)
FMC#1 HPC xxx MHz LVDS GBTCLK0
AC coupling on Mezz
FMC#1 HPC CLK2_M2C
(LVDS)
ICS
854104
ICS
854104
100 MHz LVDS
FMC#2 LPC xxx MHz GBTCLK0 LVDS
AC coupling on Mezz
ICS874001
250 MHz LVDS
No Connect
No Connect
No Connect
(LVDS)
To FPGA CLK2_M2C_IO CC pin
GTX_X0Y15
GTX_X0Y14
REFCLK0
REFCLK1
GTX_X0Y13
GTX_X0Y12
GTX_X0Y11
GTX_X0Y10
REFCLK0
REFCLK1
GTX_X0Y09
GTX_X0Y08
GTX_X0Y07
GTX_X0Y06
REFCLK0
REFCLK1
GTX_X0Y05
GTX_X0Y04
PCIe Lane1
PCIe Lane 2
PCIe Lane 3
PCIe Lane 4
PCIe Lane 5
PCIe Lane 6
PCIe
PCIe Lane 7
PCIe Lane 8
FMC#1
FMC#1
FMC#1
FMC#1
PCIe
FMC#1 HPC xxx MHz LVDS GBTCLK1
AC coupling on Mezz
FMC#1 HPC CLK3_M2C
(LVDS)
ICS
854104
(LVDS)
To FPGA CLK3_M2C_IO CC pin
GTX_X0Y03
GTX_X0Y02
REFCLK0
REFCLK1
GTX_X0Y01
GTX_X0Y00
FMC#1
FMC#1
FMC#1
FMC#1
UG534_10_021012
Figure 1-10: MGT Clocking
References
See the Virtex-6 FPGA GTX Transceivers User Guide. [Ref 12]
ML605 Hardware User Guide
www.xilinx.com
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UG534 (v1.8) October 2, 2012