UG534 Datasheet, PDF (58/96 Pages) –

Chapter 1: ML605 Evaluation Board
Mode, Osc Enable, Boot EEPROM Select, and Addr Select DIP Switch S2
DIP switch S2 is a multi-purpose selector switch (Figure 1-27 and Table 1-27, page 59).
FPGA Mode: S2 switches 3, 4, and 5 control the FPGA mode (Table 1-26).
Oscillator Enable: S2 switch 1, CCLK_EXTERNAL, controls the enable pin of the 47 MHz
oscillator SiT8102 (X4). When switch 1 is closed (CCLK_EXTERNAL High), X4 drives a
47 MHz clock onto the FPGA_CCLK signal.
Boot EEPROM Select: S2 switch 2 is used to select the between the Xilinx Platform Flash or
the Numonyx Linear BPI Flash for the FPGA boot memory device.
Upper or Lower Address Select: S2 switch 6 is used to select the upper or lower half of
flash memory U4 as the source of the FPGA bitstream image. When FLASH_A23 is High,
the upper half of the address is selected. When FLASH_A23 is Low, the lower half of the
address is selected.
X-Ref Target - Figure 1-27
VCC2V5
1
1
2
2
1
2
S2
7
6
8
5
9
4
10
3
11
2
12
1
SDMX-6-X
FLASH_A23
FPGA_M2
FPGA_M1
FPGA_M0
P30_CS_SEL
CCLK EXTERNAL
1
1
1
11
1
2
2
2
22
2
Figure 1-27: Multi-Purpose Select DIP Switch S2
UG534_27_110409
Table 1-26 shows the FPGA configuration modes controlled by S2 switches 3, 4, and 5.
Table 1-26: ML605 Configuration Modes
Configuration Mode
M[2:0]
Bus Width
CCLK
Master BPI-Up
010
8, 16
Output
JTAG
101
1
Input (TCK)
Slave SelectMAP
110
8, 16, 32
Input
58
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ML605 Hardware User Guide
UG534 (v1.8) October 2, 2012