UG534 Datasheet, PDF (75/96 Pages) –

Detailed Description
FPGA Power Supply Margining
The PMBus (IIC), which provides access to the 2 x UDC9240 power controllers, can also be
accessed via FPGA I/O in addition to a dedicated header (J3), see Figure 1-33. A full
description of the UDC9240 functionality is outside the scope of this user guide. However,
this useful feature can be used, for example, to margin the FPGA and board power
supplies when evaluating a design. The System Monitor provides accurate measurements
of the on-chip supply voltages as the FPGA supplies are margined. The PMBus (and fan)
connections are shown in Figure 1-32.
X-Ref Target - Figure 1-33
TI_V3P3
PMBus Connector
J3
NC
12
NC
NC
34
NC
NC
56
78
9 10
R301
100K
5%
R299
100K
5%
R335
1.0M
5%
AGND1
DGND1
9240
BANK 34
6vlx240tff1156
R300
100K
5%
UDC9240
PMBUS_ALERT 35
PMBUS_DATA 20
PMBUS_CLK 19
PMBUS_CTRL 36
IO_L11N_SRCC_34_AJ9
IO_L11P_SRCC_34_AH9
IO_L10N_MRCC_34_AB10
IO_L10P_MRCC_34_AC10
IO_L9N_MRCC_34_M10
IO_L9P_MRCC_34_L10
AJ9
AH9
AB10
AC10
M10
L10
PMBUS_CTRL_LS
PMBUS_ALERT_LS
PMBUS_DATA_LS
PMBUS_CLK_LS
SM_FAN_TACH
SM_FAN_PWM
UG534_35_081209
Figure 1-33: UDC9240 PMBus Access
System Monitor ML605 Demonstration Design
The various features described in this section are easily evaluated using a MicroBlaze™
based reference designed provided with the ML605 Evaluation Board. This reference
design supports a UART based interface using a terminal program such as Hyperterminal
to provide information on the FPGA power supplies, temperature, and power
consumption. In addition, the UART interface can be used to margin the FPGA supplies
over the PMBus.
The System Monitor functionality can also be accessed at any time via JTAG using the
ChipScope Pro Analyzer tool without design modifications or cores inserted into a user
design. The ChipScope Pro Analyzer tool automatically connects to the System Monitor
via a JTAG cable after a connection is established.
References
For more information on using the System Monitor and an overview of the tool support for
this feature, see the Virtex-6 FPGA System Monitor User Guide. [Ref 15]
ML605 Hardware User Guide
www.xilinx.com
75
UG534 (v1.8) October 2, 2012