UG534 Datasheet, PDF (49/96 Pages) –

Detailed Description
FPGA INIT and DONE LEDs
The typical Xilinx FPGA power up and configuration status LEDs are present on the
ML605.
The red INIT LED DS31 comes on momentarily after the FPGA powers up and during its
internal power-on process. The DONE LED DS13 comes on after the FPGA programming
bitstream has been downloaded and the FPGA successfully configured.
X-Ref Target - Figure 1-17
VCC2V5
VCC2V5
FPGA INIT B
1 _R419
330
Q14
1
FPGA_DONE
5%
2 _1/16W
NDS336P
1 _R3
27.4
2 ^1%
1/16W
1 _R4
27.4
2
1%
1/16W
Figure 1-17: FPGA INIT and DONE LEDs
Table 1-20: FPGA INIT and DONE LED Connections
FPGA U1 Pin Schematic Net Name Controlled LED
P8
FPGA_INIT_B
DS31 INIT, Red
R8
FPGA_DONE
DS13 DONE, Green
UG534_17_050510
17. User I/O
The ML605 provides the following user and general purpose I/O capabilities:
• User LEDs (8) with parallel wired GPIO male pin header
• User Pushbutton (5) switches with associated direction LEDs
• CPU Reset pushbutton switch
• User DIP switch (8-pole)
• User SMA GPIO
• LCD Display (16 char x 2 lines)
ML605 Hardware User Guide
www.xilinx.com
49
UG534 (v1.8) October 2, 2012