W958D6DB Datasheet, PDF (9/57 Pages) Winbond – Low-power features

W958D6DB
256Mb Async./Burst/Sync./A/D MUX
8. FUNCTIONAL DESCRIPTION
In general, ADMUX PSRAM devices are high-density alternatives to SRAM and Pseudo SRAM products, popular in
low-power, portable applications. Both devices implement a multiplexed address/data bus. This multiplexed
configuration supports greater bandwidth through the x16 data bus, yet still reduces the required signal count. The
ADMUX PSRAM bus interface supports both asynchronous and burst mode transfers.
8.1 Power Up Initialization
ADMUX PRAM products include an on-chip voltage sensor used to launch the power-up initialization process.
Initialization will configure the BCR and the RCR with their default settings. VCC and VCCQ must be applied
simultaneously. When they reach a stable level at or above 1.7V, the device will require 150μs to complete its self-
initialization process. During the initialization period, CE# should remain HIGH. When initialization is complete, the
device is ready for normal operation.
8.1.1 Power-Up Initialization Timing
Vcc=1.7v
Vcc
VccQ
tpu>=150us
Device Initialization
Device ready for
normal operation
8.2 Bus Operating Modes
This asynchronous/burst ADMUX PSRAM products incorporate a burst mode interface found on Flash products
targeting low-power, wireless applications. This bus interface supports asynchronous, and burst mode read and write
transfers. The specific interface supported is defined by the value loaded into the BCR.
8.2.1 Asynchronous Modes
Using industry-standard SRAM control signals (CE#, ADV#, OE#, WE#, and LB#/UB#). READ operations are initiated
by bringing CE#, ADV#, and LB#/UB# LOW while keeping OE# and WE# HIGH, and driving the address onto the
A/DQ bus. ADV# is taken HIGH to capture the address, and OE# is taken LOW. Valid data will be driven out of the
I/Os after the specified access time has elapsed.
WRITE operations occur when CE#, ADV#, WE#, and LB#/UB# are driven LOW with the address on the A/DQ bus.
ADV# is taken HIGH to capture the address, then the WRITE data is driven onto the bus. During asynchronous
WRITE operations, the OE# level is a ―Don't Care,‖ and WE# will override OE#; however, OE# must be HIGH while
the address is driven onto the A/DQ bus. The data to be written is latched on the rising edge of CE#, WE#, UB#, or
LB# (whichever occurs first).
During asynchronous operation with burst mode enabled, the CLK input must be held static (HIGH or LOW). WAIT will
be driven during asynchronous READs, and its state should be ignored. WE# LOW time must be limited to tCEM.
Publication Release Date : June 27 ,2013
-9-
Revision : A01-003