W958D6DB Datasheet, PDF (6/57 Pages) Winbond – Low-power features

W958D6DB
5. PIN DESCRIPTION
5.1 Signal Description
256Mb Async./Burst/Sync./A/D MUX
Symbol
Type
Description
A[max:16]
Input
Address inputs: Inputs for addresses during READ and WRITE operations. Addresses are
internally latched during READ and WRITE cycles. The address lines are also used to define
the value to be loaded into the BCR or the RCR. A[max:16]= A[23:16] (256Mb).
Clock: Synchronizes the memory to the system operating frequency during synchronous
CLK
(Note 1)
Input
operations. When configured for synchronous operation, the address is latched on the first
rising CLK edge when ADV# is active. CLK must be static (HIGH or LOW) during
asynchronous access READ and WRITE operations when burst mode is enabled.
ADV#
(Note 1)
Input
Address valid: Indicates that a valid address is present on the address inputs. Addresses are
latched on the rising edge of ADV# during asynchronous READ and WRITE operations.
CRE
Input
Control register enable: When CRE is HIGH, WRITE operations load the RCR or BCR, and
READ operations access the RCR, BCR, or DIDR.
Chip enable: Activates the device when LOW. When CE# is HIGH, the device is disabled and
CE#
Input
goes into standby mode.
OE#
Input
Output enable: Enables the output buffers when LOW. When OE# is HIGH, the output buffers
are disabled.
WE#
Input
Write enable: Determines if a given cycle is a WRITE cycle. If WE# is LOW, the cycle is a
WRITE to either a configuration register or to the memory array.
LB#
Input
Lower byte enable. DQ[7:0].
UB#
Input
Upper byte enable. DQ[15:8].
Address/data I/Os: These pins are a multiplexed address/data bus. As inputs for addresses,
A/DQ[15:0]
these pins behave as A[15:0]. A[0] is the LSB of the 16-bit word address within the
Input/Output
CellularRAM device. Address, RCR, and BCR values are loaded with ADV# LOW. Data is
input or output when ADV# is HIGH.
WAIT: Provides data-valid feedback during burst READ and WRITE operations. WAIT is used
WAIT
(Note 1)
Output
to arbitrate collisions between refresh and READ/WRITE operations. WAIT is also asserted at
the end of a row unless wrapping within the burst length. WAIT should be ignored during
asynchronous operations. WAIT is High-Z when CE# is HIGH.
NC
—
Reserved for future use.
VCC
Supply
Device power supply: Power supply for device core operation.
VCCQ
Supply
I/O power supply: Power supply for input/output buffers.
VSS
Supply
VSS must be connected to ground.
VSSQ
Supply
VSSQ must be connected to ground.
Notes: 1. When using asynchronous mode exclusively, CLK can be tied to VSSQ or VCCQ . WAIT should be ignored during
asynchronous mode operations.
Publication Release Date : June 27 ,2013
-6-
Revision : A01-003