W958D6DB Datasheet, PDF (8/57 Pages) Winbond – Low-power features

W958D6DB
7. INSTRUCTION SET
7.1 Bus Operation
Asynchronous
Mode BCR[15] =
Power
1 (default)
Read
Active
256Mb Async./Burst/Sync./A/D MUX
LB#/
CLK ADV# CE# OE# WE# CRE _UB# WAIT*2 A/DQ[15:0]*3 Notes
X
L
L
H
L
L
Low-Z
Data out
4
Write
Active
X
L
X
L
L
L
High-Z
Data in
4
Standby
Standby
H or L
X
H
X
X
L
X
High-Z
High-Z
5, 6
No operation
Configuration
register WRITE
Configuration
register READ
DPD
Burst Mode
BCR[15] = 0
Read
Idle
Active
X
X
L
X
X
L
X
Low-Z
X
4, 6
X
L
H
L
H
X
Low-Z
High-Z
Active
X
L
L
H
H
L
Low-Z Config. reg. out
Deep power-
down
Power
X
X
H
X
X
X
X
High-Z
High-Z
10
CLK*1 ADV# CE# OE# WE# CRE ^LB#/ WAIT*2 A/DQ[15:0]*3 Notes
UB#
Active
H or L
L
L
H
L
L
Low-Z
Data out
4, 7
Write
Active
H or L
L
X
L
L
L
High-Z
Data in
4
Standby
Standby
H or L
X
H
X
X
L
X
High-Z
High-Z
5, 6
No operation
Idle
H or L
X
L
X
X
L
X
Low-Z
X
4, 6
Initial burst READ
Active
L
L
X
H
L
L
Low-Z
Address
4, 8
Initial burst WRITE
Active
L
L
H
L
L
X
Low-Z
Address
4, 8
Burst continue
Active
Data in or Data
H
L
X
X
X
L
Low-Z
4, 8
out
Configuration
register WRITE
Active
L
L
H
L
H
X
Low-Z
High-Z
8, 9
Configuration
register READ
Active
L
L
L
H
H
L
Low-Z Config. reg. out 8, 9
DPD
Deep power-
L
X
H
X
X
X
X
High-Z
High-Z
10
down
Notes: 1. With burst mode enabled, CLK must be static (HIGH or LOW) during asynchronous READs and asynchronous WRITEs and to achieve
standby power during standby mode.
2.The WAIT polarity is configured through the bus configuration register (BCR[10]).
3.When LB# and UB# are in select mode (LOW), DQ[15:0] are enabled. When only LB# is in select mode, DQ[7:0] are enabled. When only
UB# is in the select mode, DQ[15:8] are enabled.
4.The device will consume active power in this mode whenever addresses are changed.
5.When the device is in standby mode, address inputs and data inputs/outputs are internally isolated from any external influence.
6.VIN = VCCQ or 0V; all device balls must be static (unswitched) in order to achieve standby current.
7.When the BCR is configured for synchronous mode, synchronous READ and WRITE and asynchronous WRITE and READ are supported.
8.Burst mode operation is initialized through the bus configuration register (BCR[15]).
9.Initial cycle. Following cycles are the same as BURST CONTINUE. CE# must stay LOW for the equivalent of a single-word burst (as
indicated by WAIT).
10. DPD is initiated when CE# transitions from LOW to HIGH after writing RCR[4] to 0. DPD is maintained until CE# transitions from HIGH to
LOW.
Publication Release Date : June 27 ,2013
-8-
Revision : A01-003