W958D6DB Datasheet, PDF (16/57 Pages) Winbond – Low-power features

W958D6DB
256Mb Async./Burst/Sync./A/D MUX
8.4 Registers
Two user-accessible configuration registers define the device operation. The bus configuration register (BCR) defines
how the ADMUX PSRAM interacts with the system memory bus and is nearly identical to its counterpart on burst
mode Flash devices. The refresh configuration register (RCR) is used to control how refresh is performed on the
DRAM array. These registers are automatically loaded with default settings during power-up, and can be updated any
time the devices are operating in a standby state.
A DIDR provides information on the device manufacturer, CellularRAM generation, and the specific device
configuration. The DIDR is read-only.
8.4.1 Access Using CRE
The registers can be accessed using either a synchronous or an asynchronous operation when the control register
enable (CRE) input is HIGH. When CRE is LOW, a READ or WRITE operation will access the memory array. The
configuration register values are written via addresses A[max:16] and ADQ[15:0]. In an asynchronous WRITE, the
values are latched into the configuration register on the rising edge of ADV#, CE#, or WE#, whichever occurs first; LB#
and UB# are ―Don’t Care.‖ The BCR is accessed when A[19:18] are 10b; the RCR is accessed when A[19:18] are 00b.
The DIDR is read when A[19:18] are 01b. For reads, address inputs other than A[19:18] are ―Don’t Care,‖ and register
bits 15:0 are output on DQ[15:0]. Immediately after performing a configuration register READ or WRITE operation,
reading the memory array is highly recommended.
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Publication Release Date : June 27 ,2013
Revision : A01-003