W958D6DB Datasheet, PDF (35/57 Pages) Winbond – Low-power features

W958D6DB
256Mb Async./Burst/Sync./A/D MUX
10.1.2 Burst READ Cycle Timing Requirements
All tests performed with outputs configured for default setting of half drive strength, (BCR[5:4] = 01b).
Parameter
133 MHz 104 MHz
Symbol
Unit Note
Min Max Min Max
Address access time (fixed latency)
tAA
70
70
ns
ADV# access time (fixed latency)
tAADV
70
70
ns
Burst to READ access time (variable latency)
tABA
35.5
35.9
ns
CLK to output delay
tACLK
5.5
7
ns
Address hold from ADV# HIGH (fixed latency)
tAVH
2
2
ns
Burst OE# LOW to output delay
tBOE
20
20
ns
CE# HIGH between subsequent burst or mixed-mode operations
tCBPH
5
5
ns
1
Maximum CE# pulse width
tCEM
4
4
µs
1
CLK period
tCLK
7.5
9.62
ns
Chip select access time (fixed latency)
tCO
70
70
ns
CE# setup time to active CLK edge
tCSP
2.5
3
ns
Hold time from active CLK edge
tHD
1.5
2
ns
Chip disable to DQ and WAIT High-Z output
tHZ
7
7
ns
2
CLK rise or fall time
tKHKL
1.2
1.6
ns
CLK to WAIT valid
tKHTL
5.5
7
ns
Output HOLD from CLK
tKOH
2
2
ns
CLK HIGH or LOW time
tKP
3
3
ns
Output disable to DQ High-Z output
tOHZ
7
7
ns
2
Output enable to Low-Z output
tOLZ
3
3
ns
3
Setup time to active CLK edge
tSP
2
3
ns
Notes: 1. A refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two
conditions: a) clocked CE# HIGH, or b) CE# HIGH for longer than 15ns.
2. Low-Z to High-Z timings are tested with the circuit. The High-Z timings measure a 100mV transition from either VOH or
VOL toward VCCQ/2.
3. High-Z to Low-Z timings are tested with the circuit. The Low-Z timings measure a 100mV transition away from the High-Z
(VCCQ/2) level toward either VOH or VOL..
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Publication Release Date : June 27 ,2013
Revision : A01-003