W958D6DB Datasheet, PDF (27/57 Pages) Winbond – Low-power features

W958D6DB
8.4.3.9 WAIT Configuration During Burst Operation
256Mb Async./Burst/Sync./A/D MUX
CLK
WAIT
WAIT
BCR[8]=0
Data vaild in current cycle
BCR[8]=1
Data vaild in next cycle
A/DQ[15:0]
Initial latency _D0
D1
D2
D3
Note : Signals shown are for WAIT active LOW, no wrap.
End of row
Don’t care
8.4.3.10 Latency Counter (BCR[13:11]) Default = Three Clock Latency
The latency counter bits determine how many clocks occur between the beginning of a READ or WRITE operation and
the first data value transferred. For allowable latency codes, see the following tables and figures.
8.4.3.11 Initial Access Latency (BRC[14]) Default = Variable
Variable initial access latency outputs data after the number of clocks set by the latency counter. However, WAIT must
be monitored to detect delays caused by collisions with refresh operations.
Fixed initial access latency outputs the first data at a consistent time that allows for worst-case refresh collisions. The
latency counter must be configured to match the initial latency and the clock frequency. It is not necessary to monitor
WAIT with fixed initial latency. The burst begins after the number of clock cycles configured by the latency counter.
8.4.3.12 Allowed Latency Counter Settings in Variable Latency Mode
BCR[13:11]
Latency
Configuration
Code
Latency *1
Normal
Maximum
with Refresh
Collision
Max Input CLK Frequency (MHz)
133
104
010
2 (3 clocks)
2
4
66 (15ns)
66 (15ns)
011
3(4clocks)—default
3
6
104 (9.62ns)
104 (9.62ns)
100
4 (5 clocks)
4
8
133 (7.5ns)
—
Others
Reserved
—
—
—
—
Notes: 1.Latency is the number of clock cycles from the initiation of a burst operation until data appears. Data is transferred on the
next clock cycle.
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Publication Release Date : June 27 ,2013
Revision : A01-003