W958D6DB Datasheet, PDF (31/57 Pages) Winbond – Low-power features

W958D6DB
8.4.4.3 Address Patterns for PAR (RCR [4] = 1)
RCR[2] RCR[1] RCR[0] Active Section
0
0
0
Full die
0
0
1
One-half of die
0
1
0
One-quarter of die
0
1
1
One-eighth of die
1
0
0
None of die
1
0
1
One-half of die
1
1
0
One-quarter of die
1
1
1
One-eighth of die
256Mb Async./Burst/Sync./A/D MUX
Address Space
000000h–FFFFFFh
000000h–7FFFFFh
000000h–3FFFFFh
000000h–1FFFFFh
0
800000h–FFFFFFh
C00000h–FFFFFFh
E00000h–FFFFFFh
Size
16 Meg x 16
8 Meg x 16
4 Meg x 16
2 Meg x 16
0 Meg x 16
8 Meg x 16
4 Meg x 16
2 Meg x 16
Density
256Mb
128Mb
64Mb
32Mb
0Mb
128Mb
64Mb
32Mb
8.4.4.4 Deep Power-Down (RCR[4]) Default = DPD Disabled
The deep power-down bit enables and disables all refresh-related activity. This mode is used if the system does not
require the storage provided by the ADMUX PSRAM device. Any stored data will become corrupted when DPD is
enabled. When refresh activity has been re-enabled, the CellularRAM device will require 150μs to perform an
initialization procedure before normal operations can resume.
Deep power-down is enabled by setting RCR[4] = 0 and taking CE# HIGH. DPD can be enabled using CRE or the
software sequence to access the RCR. Taking CE# LOW for at least 10μs disables DPD and sets RCR[4] = 1; it is not
necessary to write to the RCR to disable DPD. BCR and RCR values (other than BCR[4]) are preserved during
DPD.
8.4.5 Device Identification Register
The DIDR provides information on the device manufacturer, CellularRAM generation, and the specific device
configuration. This register is read-only.
The DIDR is accessed with CRE HIGH and A[19:18] = 01b, or through the register access software sequence with
ADQ = 0002h on the third cycle.
8.4.5.1 Device Identification Register Mapping
Bit Field
DIDR[15]
DIDR[14:11]
Field name
Row length
Device version
Length Bit Setting Version Bit Setting
Options 256 words
1b
1st
0000b
2nd
0001b
DIDR[10:8]
Device density
Density Bit Setting
256Mb
100b
DIDR[7:5]
DIDR[4:0]
CellularRAM generation
Vendor ID
Generation Bit Setting Vendor Bit Setting
CR1.5
010b Winbond 00110b
8.4.5.2 Virtual Chip Enable Function:
A 512Mb device can be implemented by a MCP consisting of two stacked 256Mb devices with Virtual Chip Enable
function. By proper configuration, one 2568Mb device of the MCP is mapped to the lower 256Mb memory space of the
512Mb device and the another one 256Mb device is mapped to the upper 256Mb memory space of the 512Mb device.
The 256Mb device with Virtual Chip Enable function provides a VCE input pin which is controlled by the A24 (the MSB
of address bus of 512Mb memory space). When the 256Mb device is mapped to the lower 256Mb memory space, the
device will be active if A24 is low. When the 256Mb device is mapped to the upper 256Mb memory space, the device
will be active if A24 is high.
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Publication Release Date : June 27 ,2013
Revision : A01-003