W958D6DB Datasheet, PDF (37/57 Pages) Winbond – Low-power features

W958D6DB
10.1.4 Burst WRITE Cycle Timing Requirements
Parameter
256Mb Async./Burst/Sync./A/D MUX
Symbol
133 MHz
104 MHz
Unit Note
Min Max Min Max
Address and ADV# LOW setup time
tAS
0
0
ns
1
Address HOLD from ADV# HIGH (fixed latency)
CE# HIGH between subsequent burst or mixed-mode
operations
Maximum CE# pulse width
tAVH
tCBPH
tCEM
2
2
5
5
4
ns
ns
2
4
µs
2
Clock period
tCLK
7.5
9.62
ns
CE# setup to CLK active edge
tCSP
2.5
3
ns
Hold time from active CLK edge
tHD
1.5
2
ns
Chip disable to WAIT High-Z output
tHZ
7
7
ns
3
CLK rise or fall time
tKHKL
1.2
1.6
ns
Clock to WAIT valid
tKHTL
5.5
7
ns
Output HOLD from CLK
tKOH
2
2
ns
CLK HIGH or LOW time
tKP
3
3
ns
Setup time to activate CLK edge
tSP
2
3
ns
Notes: 1.tAS required if tCSP > 20ns.
2.A refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two
conditions: a) clocked CE# HIGH, or b) CE# HIGH for longer than 15ns.
3.Low-Z to High-Z timings are tested with the circuit. The High-Z timings measure a 100mV transition from either VOH or
VOL toward VCCQ/2.
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Publication Release Date : June 27 ,2013
Revision : A01-003