W958D6DB Datasheet, PDF (13/57 Pages) Winbond – Low-power features

W958D6DB
256Mb Async./Burst/Sync./A/D MUX
The size of a burst can be specified in the BCR either as a fixed length or continuous. Fixed-length bursts consist of 4,
8, 16, or 32 words. Continuous bursts have the ability to start at a specified address and burst to the end of the
address. It goes back to the first address and continues to burst when continuous bursts meet the end of address.
The latency count stored in the BCR defines the number of clock cycles that elapse before the initial data value is
transferred between the processor and ADMUX PSRAM device. The initial latency for READ operations can be
configured as fixed or variable (WRITE operations always use fixed latency). Variable latency allows the ADMUX
PSRAM to be configured for minimum latency at high clock frequencies, but the controller must monitor WAIT to
detect any conflict with refresh cycles.
Fixed latency outputs the first data word after the worst-case access delay, including allowance for refresh collisions.
The initial latency time and clock speed determine the latency count setting. Fixed latency is used when the controller
cannot monitor WAIT. Fixed latency also provides improved performance at lower clock frequencies.
The WAIT output asserts when a burst is initiated, and de-asserts to indicate when data is to be transferred into (or out
of) the memory. WAIT will again be asserted at the boundary of the row, unless wrapping within the burst length. With
wrap off, the ADMUX PSRAM device will restore the previous row’s data and access the next row, WAIT will be de-
asserted, and the burst can continue across the row boundary. If the burst is to terminate at the row boundary, CE#
must go HIGH within 2 clocks of the last data. CE# must go HIGH before any clock edge following the last word of a
defined-length burst WRITE.
The CE# LOW time is limited by refresh considerations. CE# must not stay LOW longer than tCEM. If a burst
suspension will cause CE# to remain LOW for longer than tCEM, CE# should be taken HIGH and the burst restarted
with a new CE# LOW/ADV# LOW cycle.
8.2.2.3 Refresh Collision During Variable-Latency READ Operation
CLK
VIH
VIL
A[max:16]
VIH
VIL
ADV#
VIH
VIL
Valid
Address
CE#
VIH
VIL
OE#
VIH
VIL
WE#
VIH
VIL
LB#/UB#
VIH
VIL
A/DQ[15:0] ^VIH
VIL
VOH
WAIT _VOL
Valid
Address
High-z
VOH
VOL
D0
D1
D2
D3
Additional WAIT satates inserted to allow refresh completion
Undefined
Don’t Care
Note : Non-default BCR settings for refresh collision during variable-latency READ operation : latency code 2(3 clocks) , WAIT
active LOW , WAIT asserted during delay.
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Publication Release Date : June 27 ,2013
Revision : A01-003