W958D6DB Datasheet, PDF (34/57 Pages) Winbond – Low-power features

W958D6DB
256Mb Async./Burst/Sync./A/D MUX
10. TIMING REQUIRMENTS
10.1 Read, Write Timing Requirements
10.1.1 Asynchronous READ Cycle Timing Requirements
All tests performed with outputs configured for default setting of half drive strength, (BCR[5:4] = 01b).
Parameter
Symbol Min Max Unit Note
Address access time
tAA
70
ns
ADV# access time
tAADV
70
ns
Address hold from ADV# HIGH
tAVH
2
ns
Address setup to ADV# HIGH
tAVS
5
ns
LB#/UB# access time
tBA
70
ns
LB#/UB# disable to DQ High-Z Output
tBHZ
7
ns
1
Chip select access time
tCO
70
ns
CE# LOW to ADV# HIGH
tCVS
7
ns
Chip disable to DQ and WAIT High-Z output
tHZ
7
ns
1
Output enable to valid output
tOE
20
ns
OE# LOW to WAIT valid
tOEW
1
7.5
ns
Output disable to DQ High-Z output
tOHZ
7
ns
1
Output enable to Low-Z output
tOLZ
3
ns
2
ADV# pulse width
tVP
5
ns
Notes: 1. Low-Z to High-Z timings are tested with AC Output Load Circuit. The High-Z timings measure a 100mV transition from
either VOH or VOL toward VCCQ/2.
2. High-Z to Low-Z timings are tested with the circuit. The Low-Z timings measure a 100mV transition away from the High-Z
(VCCQ/2) level toward either VOH or VOL.
- 34 -
Publication Release Date : June 27 ,2013
Revision : A01-003