W958D6DB Datasheet, PDF (15/57 Pages) Winbond – Low-power features

W958D6DB
256Mb Async./Burst/Sync./A/D MUX
8.2.5 LB#/ UB# Operation
The LB# enable and UB# enable signals support byte-wide data WRITEs. During WRITE operations, any disabled
bytes will not be transferred to the RAM array and the internal value will remain unchanged. During an asynchronous
WRITE cycle, the data to be written is latched on the rising edge of CE#, WE#, LB#, or UB#, whichever occurs first.
LB# and UB# must be LOW during READ cycles.
When both the LB# and UB# are disabled (HIGH) during an operation, the device will disable the data bus from
receiving or transmitting data. Although the device will seem to be deselected, it remains in an active mode as long as
CE# remains LOW.
8.3 Low Power Operation
8.3.1 Standby Mode Operation
During standby, the device current consumption is reduced to the level necessary to perform the DRAM refresh
operation. Standby operation occurs when CE# is HIGH. The device will enter a reduced power state upon completion
of a READ or WRITE operation, or when the address and control inputs remain static for an extended period of time.
This mode will continue until a change occurs to the address or control inputs.
8.3.2 Temperature Compensated Refresh
Temperature-compensated refresh (TCR) allows for adequate refresh at different temperatures. This ADMUX
PSRAM device includes an on-chip temperature sensor that automatically adjusts the refresh rate according to the
operating temperature. The device continually monitors the temperature to select an appropriate self-refresh rate.
8.3.3 Partial-Array Refresh
Partial-array refresh (PAR) restricts refresh operation to a portion of the total memory array. This feature enables the
device to reduce standby current by refreshing only that part of the memory array required by the host system. The
refresh options are full array, one-half array, one-quarter array, one-eighth array, or none of the array. The mapping of
these partitions can start at either the beginning or the end of the address map . READ and WRITE operations to
address ranges receiving refresh will not be affected. Data stored in addresses not receiving refresh will become
corrupted. When additional portions of the array need to be re-enabled, the new portions are available immediately
after the completion of the WRITE cycle that updates the RCR with the new configuration.
8.3.4 Deep Power-Down Operation
Deep power-down (DPD) operation disables all refresh-related activity. This mode is used if the system does not
require the storage provided by the ADMUX PSRAM device. Any stored data will become corrupted when DPD is
enabled. When refresh activity has been re-enabled, the ADMUX PSRAM device will require 150μs to perform an
initialization procedure before normal operations can resume. During this 150μs period, the current consumption will
be higher than the specified standby levels, but considerably lower than the active current specification.
DPD can be enabled by writing to the RCR using CRE or the software access sequence; DPD starts when CE# goes
HIGH. DPD is disabled the next time CE# goes LOW and stays LOW for at least 10μs.
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Publication Release Date : June 27 ,2013
Revision : A01-003