W958D6DB Datasheet, PDF (26/57 Pages) Winbond – Low-power features

W958D6DB
256Mb Async./Burst/Sync./A/D MUX
8.4.3.5 Drive Strength (BCR[5:4]) Default = Outputs Use Half-Drive Strength
The output driver strength can be altered to full, one-half, or one-quarter strength to adjust for different data bus
loading scenarios. The reduced-strength options are intended for stacked chip (Flash + ADMUX PSRAM )
environments when there is a dedicated memory bus. The reduced-drive-strength option minimizes the noise
generated on the data bus during READ operations. Full output drive strength should be selected when using a
discrete ADMUX PSRAM device in a more heavily loaded data bus environment. Outputs are configured at half-drive
strength during testing.
8.4.3.6 Table of Drive Strength
BCR[5]
BCR[4]
0
0
0
1
1
0
1
1
Drive Strength
Full
1/2 (default)
1/4
Impedance Typ (Ω)
25–30
50
100
Reserved
Use Recommendation
CL = 30pF to 50pF
CL = 15pF to 30pF
CL = 15pF or lower
8.4.3.7 WAIT Configuration. (BCR[8])
Default =WAIT Transitions 1 Clock Before Data Valid/ Invalid
The WAIT configuration bit is used to determine when WAIT transitions between the asserted and the de-asserted
state with respect to valid data presented on the data bus. The memory controller will use the WAIT signal to
coordinate data transfer during synchronous READ and WRITE operations. When BCR[8] = 0, data will be valid or
invalid on the clock edge immediately after WAIT transitions to the de-asserted or asserted state, respectively. When
BCR[8] = 1, the WAIT signal transitions one clock period prior to the data bus going valid or invalid.
8.4.3.8 WAIT Polarity (BCR[10])
Default = WAIT Active HIGH
The WAIT polarity bit indicates whether an asserted WAIT output should be HIGH or LOW. This bit will determine
whether the WAIT signal requires a pull-up or pull-down resistor to maintain the de-asserted state.
The default value is BCR[10]=1, indicating WAIT active HIGH.
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Publication Release Date : June 27 ,2013
Revision : A01-003