W83877TF Datasheet, PDF (58/154 Pages) Winbond – I/O chip disk drive adapter

W83877TF
4.2.6 Bit Map of Parallel Port and EPP Registers
REGISTER
7
6
5
4
Data Port (R/W)
Status Buffer (Read)
PD7 PD6 PD5 PD4
BUSY ACK ^{PE SLCT}
Control Swapper (Read) 1
Control Latch (Write)
1
1
1 IRQEN
1 DIR IRQ
EPP Address Port
(R/W)
PD7 PD6 PD5 PD4
EPP Data Port 0 (R/W) PD7 PD6 PD5 PD4
EPP Data Port 1 (R/W) PD7 PD6 PD5 PD4
EPP Data Port 2 (R/W) PD7 PD6 PD5 PD4
EPP Data Port 3 (R/W) PD7 PD6 PD5 PD4
3
PD3
ERROR
SLIN
SLIN
PD3
PD3
PD3
PD3
PD3
2
PD2
1
INIT
INIT
PD2
PD2
PD2
PD2
PD2
1
0
PD1
PD0
1
TMOUT
AUTOFD STROBE
AUTOFD STROBE
PD1
PD0
PD1
PD0
PD1
PD0
PD1
PD0
PD1
PD0
4.2.7 EPP Pin Descriptions
EPP NAME TYPE
EPP DESCRIPTION
nWrite
O Denotes an address or data read or write operation.
PD<0:7>
I/O Bi-directional EPP address and data bus.
Intr
I Used by peripheral device to interrupt the host.
nWait
I Inactive to acknowledge that data transfer is completed. Active to
indicate that the device is ready for the next transfer.
PE
I Paper end; same as SPP mode.
Select
I Printer selected status; same as SPP mode.
nDStrb
O This signal is active low. It denotes a data read or write operation.
nError
I Error; same as SPP mode.
nInits
O This signal is active low. When it is active, the EPP device is reset to its
initial operating mode.
nAStrb
O This signal is active low. It denotes an address read or write operation.
4.2.8 EPP Operation
When the EPP mode is selected in the configuration register, the standard and bi-directional modes
are also available. The PDx bus is in the standard or bi-directional mode when no EPP read, write, or
address cycle is currently being executed. In this condition all output signals are set by the SPP
Control Port and the direction is controlled by DIR of the Control Port.
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Publication Release Date: March 1998
Version 0.61