W83877TF Datasheet, PDF (138/154 Pages) Winbond – I/O chip disk drive adapter

W83877TF
8.2.53 Bit Map Configuration Registers
Table 8-1: Bit Map of Configuration Registers
Power-on
Register Reset Value
D7
D6
D5
D4
D3
D2
CR0
0000 0000
0
0
0
0
PRTMODS1
PRTMODS0
CR1
0000 0000
ABCHG
0
0
0
0
0
CR2
0000 0000
0
0
0
0
0
0
CR3
0011 0000
0
0
EPPVER
0
0
0
CR4
0000 0000
PRTPWD
0
URAPWD
URBPWD
PRTTRI
0
CR5
CR6
CR7
CR8
0000 0000
0000 0000
0000 0000
0000 0000
0
0
FDD D T1
0
0
0
FDD D T0
0
0
SEL4FDD
FDD C T1
DISFDDWR
0
FIPURDWN
FDD C T0
SWWP
ECPFTHR3
FDCPWD
FDD B T1
MEDIA 1
ECPFTHR2
0
FDD B T0
MEDIA 0
CR9
CRA
CRB
0000 1010
0000 0000
0000 1100
PRTMODS2
0
0
LOCKREG
0
Tx4WC
EN3MODE
0
Rx4WC
0
0
ENIFCHG
CHIP ID 3
0
IDENT
CHIP ID 2
0
MFM
CRC
CRD
0010 1000
1010 0011
TURA
SIRTX1
TURB
SIRTX0
HEFERE
SIRRX1
0
SIRRX0
URIRSEL
HDUPLX
0
IRMODE2
CR10
CR11
CR12
CR13
CR14
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
GIO0AD7
G0CADM1
GIO1AD7
G1CADM1
GIOP0MD2
GIO0AD6
G0CADM0
GIO1AD6
G1CADM0
GIOP0MD1
GIO0AD5
0
GIO1AD5
0
GIOP0MD0
GIO0AD4
0
GIO1AD4
0
GIO0CSH
GIO0AD3
0
GIO1AD3
0
GCS0IOR
GIO0AD2
GIO0AD10
GIO1AD2
GIO1AD10
GCS0IOW
CR15
CR16
0000 0000
00ss 0s0s¹
GIOP1MD2
0
GIOP1MD1
0
GIOP1MD0
G1IQSEL
GIO1CSH
G0IQSEL
GCS1IOR
0
GCS1IOW
PNPCVS
CR17
CR18
CR19
CR20
CR23
CR24
CR25
CR26
CR27
CR28
CR29
0000 0000
0000 0000
0000 0000
1111 1100²
1101 1110²
1111 1110²
1011 1110²
0010 0011²
0000 0101²
0100 0011²
0110 0000²
0
SHARH
0
FDCAD7
PRTAD7
URAAD7
URBAD7
FDCDQS3
ECPIRQx2
URAIQS3
FDCIQS3
0
SHARG
0
FDCAD6
PRTAD6
URAAD6
URBAD6
FDCDQS2
ECPIRQx1
URAIQS2
FDCIQS2
0
SHARF
0
FDCAD5
PRTAD5
URAAD5
URBAD5
FDCDQS1
ECPIRQx0
URAIQS1
FDCIQS1
PRIRQOD
SHARE
0
FDCAD4
PRTAD4
URAAD4
URBAD4
FDCDQS0
0
URAIQS0
FDCIQS0
DSFDLGRQ
SHARD
0
FDCAD3
PRTAD3
URAAD3
URBAD3
PRTDQS3
PRTIQS3
URBIQS3
IQNIQS3
DSPRLGRQ
SHARC
0
FDCAD2
PRTAD2
URAAD2
URBAD2
PRTDQS2
PRTIQS2
URBIQS2
IQNIQS2
CR2C
0000 0000
0
0
0
0
0
CLKINSEL
CR2D
CR31
CR32
CR33
0000 0000
0000 0s00
0000 0000
0000 0000
0
SCIIRQ3
CHIPPME
PM1AD7
0
SCIIRQ2
0
PM1AD6
DIS-PRECOM1
SCIIRQ1
0
PM1AD5
DRTB 1
SCIIRQ0
0
PM1AD4
DRTB 0
0
PRTPME
PM1AD3
DIS-PRECOM0
IRQMODS
FDCPME
PM1AD2
CR34
CR35
CR36
0000 0000
0000 0000
0000 0000
GPEAD7
URACNT7
URBCNT7
GPEAD6
URACNT6
URBCNT6
GPEAD5
URACNT5
URBCNT5
GPEAD4
URACNT4
URBCNT4
GPEAD3
URACNT3
URBCNT3
GPEAD2
URACNT2
URBCNT2
CR37
CR38
CR39
CR3A
0000 0000
0000 0000
0000 0000
0000 0000
FDCCNT7
PRTCNT7
GSBCNT7
0
FDCCNT6
PRTCNT6
GSBCNT6
0
FDCCNT5
PRTCNT5
GSBCNT5
TMIN_SEL
FDCCNT4
PRTCNT4
GSBCNT4
0
FDCCNT3
PRTCNT3
GSBCNT3
0
FDCCNT2
PRTCNT2
GSBCNT2
0
CR40
0000 0000
0
0
0
0
PRTIDLSTS
FDCIDLSTS
CR41
0000 0000
0
0
0
0
PRTTRAPSTS FDCTRAPSTS
CR42
0000 0000
0
0
0
0
PRTIRQSTS FDCIRQSTS
CR43
0000 0000
0
0
0
0
0
0
CR44
0000 0000
0
0
0
0
0
0
CR45
0000 0000
0
0
0
0
PRTIRQEN
FDCIRQEN
Notes:
1. 's' means its value depends on corresponding power-on setting pin.
2. These default values are valid when CR16 bit 2 is 1 during power-on reset; They will be all 0's if CR16 bit 2 is 0.
D1
0
0
0
SUAMIDI
URATRI
ECPFTHR1
FDCTRI
FDD A T1
BOOT 1
CHIP ID 1
0
INVERTZ
RX2INV
IRMODE1
GIO0AD1
GIO0AD9
GIO1AD1
GIO1AD9
GDA0OPI
GDA1OPI
0
DSUALGRQ
SHARB
FASTA
0
PRTAD1
URAAD1
URBAD1
PRTDQS1
PRTIQS1
URBIQS1
IQNIQS1
0
DRTA 1
0
URAPME
0
GPEAD1
URACNT1
URBCNT1
FDCCNT1
PRTCNT1
GSBCNT1
SMI_EN
URAIDLSTS
URATRAPSTS
URAIRQSTS
0
0
URAIRQEN
D0
IPD
0
0
SUBMIDI
URBTRI
ECPFTHR0
0
FDD A T0
BOOT 0
CHIP ID 0
0
DRV2EN
TX2INV
IRMODE0
GIO0AD0
GIO0AD8
GIO1AD0
GIO1AD8
GDA0IPI
GDA1IPI
HEFRAS
DSUBLGRQ
SHARA
FASTB
0
PRTAD0
0
0
PRTDQS0
PRTIQS0
URBIQS0
IQNIQS0
0
DRTA 0
0
URBPME
0
0
URACNT0
URBCNT0
FDCCNT0
PRTCNT0
GSBCNT0
UPULLEN
URBIDLSTS
URBTRAPSTS
URBIRQSTS
0
0
URBIRQEN
- 112 -
Publication Release Date: March 1998
Version 0.61