W83877TF Datasheet, PDF (137/154 Pages) Winbond – I/O chip disk drive adapter

W83877TF
8.2.52 Configuration Register 45 (CR45), default=00H
When the device is in Extended Function mode and EFIR is 45H, the CR45 register can be accessed
through EFDR. The bit definitions are as follows:
765
43
21
0
URBIRQEN
URAIRQEN
FDCIRQEN
PRTIRQEN
reserved
reserved
reserved
reserved
Bit 7 - bit 4 : Reserved, fixed at 0.
Bit 3 - bit 0 : Enable bits of the SMI generation due to the device's IRQ.
These bits enable the generation of an SMI interrupt due to any IRQ of the devices respectively.
These 4 bits control the printer port, FDC, UART A, and UART B SMI logic's individually. The SMI
logic output for the IRQs is as follows:
SMI logic output = (URBIRQEN and URBIRQSTS) or (URAIRQEN and URAIRQSTS) or
(FDCIRQEN and FDCIRQSTS) or (PRTIRQEN and PRTIRQSTS)
If any device's IRQ is raised, the corresponding IRQ status bit in CR42 is set. If the device's enable
bit is set and SMI_EN(in CR3A) and CHIPPME(in CR32) is both set, then SMI interrupt occurs on the
SMI output pin.
PRTIRQEN (Bit 3):
0
disable the generation of an SMI interrupt due to the printer port's IRQ.
1
enable the generation of an SMI interrupt due to the printer port's IRQ.
FDCIRQEN (Bit 2):
0
disable the generation of an SMI interrupt due to the FDC's IRQ.
1
enable the generation of an SMI interrupt due to the FDC's IRQ.
URAIRQEN (Bit 1):
0
disable the generation of an SMI interrupt due to the UART A's IRQ.
1
enable the generation of an SMI interrupt due to the UART A's IRQ.
URBIRQEN (Bit 0):
0
disable the generation of an SMI interrupt due to the UART B's IRQ.
1
enable the generation of an SMI interrupt due to the UART B's IRQ.
- 111 -
Publication Release Date: March 1998
Version 0.61