W83877TF Datasheet, PDF (132/154 Pages) Winbond – I/O chip disk drive adapter

W83877TF
8.2.43 Configuration Register 38 (CR38), default=00H
When the device is in Extended Function mode and EFIR is 38H, the CR38 register can be accessed
through EFDR. The bit definitions are as follows:
765
43
21
0
PRTCNT0
PRTCNT1
PRTCNT2
PRTCNT3
PRTCNT4
PRTCNT5
PRTCNT6
PRTCNT7
PRTCNT7 - PRTCNT0 (Bit 7 - bit 0): printer port idle timer count.
This register is used to specify the initial value of the printer port idle timer. Once the printer port
enters the working state (that is, after any access to this device, any IRQ, and any external input), the
power down machine of the printer port reloads this count value and this idle timer counts down.
When the timer counts down to zero, printer port enters the power down state ,i.e., sleeping state. If
this register is set to 00H, the power down function will be invalid. The time resolution of this value is
minute or second, which is defined by the TMIN_SEL bit of CR3A. Note that (1). this register is valid
only when the power management function of the printer port is enabled, that is, CHIPPME=1 (CR32
bit 7) and PRTPME=1 (CR32 bit 3), (2). If the register is set to 00H, the printer port will remain in the
current state(working or sleeping).
8.2.44 Configuration Register (CR39), default=00H
When the device is in Extended Function mode and EFIR is 39H, the CR39 register can be accessed
through EFDR. The bit definitions are as follows:
765
43
21
0
GSBCNT0
GSBCNT1
GSBCNT2
GSBCNT3
GSBCNT4
GSBCNT5
GSBCNT6
GSBCNT7
GSBCNT7 - GSBCNT0 (Bit 7 - bit 0): global stand-by idle timer count.
Once all devices of the chip (including UART A, UART B, FDC and the printer port) are in the power
down state, the power down machine of W83877TF chip loads this register value and counts down.
When the timer counts to zero, the whole chip enters the power down state, i.e., sleeping state. If this
register is set to 0, the power down function will be invalid. The time resolution of this register value is
minute or second, which is defined by the TMIN_SEL bit of CR3A. Note that (1). this register is valid
when the CHIPPME = 1 (CR32 bit 7), and (2) If the register is set to 00H, W83877TF chip will remain
in the current state(working or sleeping).
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Publication Release Date: March 1998
Version 0.61