W83877TF Datasheet, PDF (107/154 Pages) Winbond – I/O chip disk drive adapter

W83877TF
8.2.13 Configuration Register C (CR0C), default = 28H
When the device is in Extended Function mode and EFIR is 0CH, the CR0C register can be accessed
through EFDR. The bit definitions are as follows:
765 43 ²¹ 0
TX2INV
RX2INV
reserved
URIRSEL
reserved
HEFERE
TURB
TURA
TURA (Bit 7):
0
the clock source of UART A is 1.8462 MHZ (24 MHz divide 13) (default)
1
the clock source of UART A is 24 MHz, it can make the baudrate of UART A up to 1.5
MHz
TURB (Bit 6):
0
the clock source of UART B is 1.8462 MHz (24 MHz divide 13) (default)
1
the clock source of UART B is 24 MHz, it can make the baudrate of UART A up to 1.5
MHz
HEFERE (Bit 5): this bit combines with HEFRAS (CR16 bit 0) to define how to enable Extended
Function Registers.
HEFRAS
0
0
1
1
HEFERE
0
1
0
1
address and value
write 88H to the location 250H
write 89H to the location 250H (default)
write 86H to the location 3F0H twice
write 87H to the location 3F0H twice
The default value of HEFERE is 1.
Bit 4: Reserved.
URIRSEL (Bit 3):
0
select UART B as IR function.
1
select UART B as normal function.
The default value of URIRSEL is 1.
Bit 2: Reserved.
RX2INV (Bit 1):
0
the SINB pin of UART B function or IRRX pin of IR function in normal condition.
1
inverse the SINB pin of UART B function or IRRX pin of IR function
TX2INV (Bit 0):
0
the SOUTB pin of UART B function or IRTX pin of IR function in normal condition.
1
inverse the SOUTB pin of UART B function or IRTX pin of IR function.
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Publication Release Date: March 1998
Version 0.61