W83877TF Datasheet, PDF (142/154 Pages) Winbond – I/O chip disk drive adapter

W83877TF
status bits which have no respective enable bit are read for special purposes. Revered or un-
implemented enable bits always return zero, and writing to these bits should have no effect.
The control bit in the control register provides some special control functions over the hardware
event, or some special control over SCI event. Reversed or un-implemented control bits always
return zero, and writing to those bits should have no effect.
Table 8-4 lists the PM1 register block and the relative locations of the registers within it. The base
address of PM1 register block is named as PM1a_EVT_BLK in the ACPI specification. The based
address should range from 01,0000,0000_b to 11,1111,0000_b ,i.e., 100H ~ 3F0H, where bit 1 and bit 0
of PM1 register block should be set to 0 and the based address is in the 16-byte alignment.
Table 8-5 lists the GPE register block and the relative locations within it. The base address of power
management event block GPE is named as GPE0_BLK in the ACPI specification. The based address
should range from 01,0000,0000_b to 11,1111,1000_b ,i.e., 100H ~ 3F8H, where bit 0 of the base
address should be set to 0 and the base address is in the 8-byte alignment.
8.4.1 Power Management 1 Status Register 1 (PM1STS1)
Register Location:
<CR33> System I/O Space
Default Value:
00h
Attribute:
Read/write
Size:
8 bits
765
43
21
0
Bit
Name
0
TMR_STS
1-3 Reserved
4
BM_STS
5
GBL_STS
6-7 Reserved
TMR_STS
Reserved
Reserved
Reserved
BM_STS
GBL_STS
Reserved
Reserved
Description
This bit is the timer carry status bit. This bit gets set anytime the bit 23 of the
24-bit counter changes(whenever the MSB changes from low to high or high
to low). While TMR_EN and TMR_STS are set a power magnet event is
raised. This bit is only set by hardware and can only be cleared by the
software writing a 1 to this bit position. Writing a 0 has no effect.
Reserved.
This is the bus master status bit. Writing a 1 to BM_CNTRL also sets
BM_STS. Writing a 1 clears this bit and also clears BM_CNTRL. Writing a 0
has no effect.
This is the global status bit. This bit is set when the BIOS want the attention
of the SCI handler. BIOS sets this bit by setting BIOS_RLS and can only be
cleared by software writing a 1 to this bit position. Writing a 1 to this bit
position also clears BIOS_RLS. Writing a 0 has no effect.
Reserved. These bits always return a value of zero.
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Publication Release Date: March 1998
Version 0.61