W83877TF Datasheet, PDF (125/154 Pages) Winbond – I/O chip disk drive adapter

W83877TF
CLKINSEL (Bit 2): Clock input frequency selection.
This pin should be reset/set according the CLKIN pin.
0
the clock source on CLKIN pin is 24 MHz.(default)
1
the clock source on CLKIN pin is 48 MHz.
Bit 1- bit 0: Reserved.
8.2.35 Configuration Register 2D (CR2D), default=00H
When the device is in Extended Function mode and EFIR is 2DH, the CR2D register can be accessed
through EFDR. The bit definitions are as follows:
765
43
21
0
DRTA0
DRTA1
DIS_PRECOMP0
DRTB0
DRTB1
DIS_PRECOMP1
reserved
reserved
This register controls the data rate selection for FDC. It also controls if precompensation is enabled.
Bit 7 - bit 6: Reserved.
DIS_PRECOMP1 (Bit 5):
This bit controls if precompensation is enabled for FDD B.
0 enable precompensation for FDD B
1 disable precompensation for FDD B
DRTB1, DRTB0 (Bit 4,3):
These two bits combining with data rate selection bits in Date Rate Register select the operational
data rate for FDD B as shown in last table.
DIS_PRECOMP0 (Bit 2):
This bit controls if precompensation is enabled for FDD A.
0 enable precompensation for FDD A
1 disable precompensation for FDD A
DRTA1, DRTA0 (Bit 1 - bit 0):
These two bits combining with data rate selection bits in Date Rate Register select the operational
data rate for FDD A as follows:
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Publication Release Date: March 1998
Version 0.61