W83877TF Datasheet, PDF (129/154 Pages) Winbond – I/O chip disk drive adapter

W83877TF
URAPME (Bit 1): UART A power management enable.
0
disable and the auto power management function.
1
enable auto power management function, if this bit and CHIPPME(CR32 bit 7)
are both set to 1.
.
URBPME (Bit 0): UART B power management enable.
0
disable the auto power management functions.
1
enable the auto power management function, if this bit and CHIPPME(CR32 bit
7) are both set to 1.
.
8.2.38 Configuration Register 33 (CR33), default=00H
When the device is in Extended Function mode and EFIR is 33H, the CR33 register can be accessed
through EFDR. The bit definitions are as follows:
765
43
21
0
reserved
reserved
PM1AD2
PM1AD3
PM1AD4
PM1AD5
PM1AD6
PM1AD7
PM1AD7 - PM1AD2 (Bit 7 - bit 2): Base address of the power management register block PM1.
This address is the base address of PM1a_EVT_BLK in the ACPI specification. The based address
should range from 01,0000,0000_b to 11,1111,0000_b ,i.e., 100H ~ 3F0H, where bit 1 and bit 0 of the
base address should be set to 0 and the based address is in the 16-byte alignment. Note that the
based address of PM1a_CNT_BLK is equal to PM1a_EVT_BLK + 4, and PM_TMR_BLK is equal to
PM1a_EVT_BLK + 8.
Bit 1 - bit 0: Reserved, fixed at 0.
8.2.39 Configuration Register 34 (CR34), default=00H
When the device is in Extended Function mode and EFIR is 34H, the CR34 register can be accessed
through EFDR. The bit definitions are as follows:
765
43
21
0
reserved
GPEAD1
GPEAD2
GPEAD3
GPEAD4
GPEAD5
GPEAD6
GPEAD7
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Publication Release Date: March 1998
Version 0.61