W83877TF Datasheet, PDF (17/154 Pages) Winbond – I/O chip disk drive adapter

W83877TF
1.2 Serial Port Interface
SYMBOL PIN
I/O
SINA
30
IN_t
SINB/IRRX1 ₄₂
RIA
31
IN_t
RIB
50
DCDA
DCDB
32
IN_t
49
DSRA
DSRB
33
IN_t
48
CTSA
CTSB
34
IN_t
47
DTRA
35
I/O_8tc
PHEFRAS
RTSA
PPNPCVS
36
I/O_8tc
SOUTA
PENFDC
38
I/O_8tc
FUNCTION
Serial Input. It is used to receive serial data from the
communication link.
Ring Indicator. An active low indicates that a ring signal is being
received by the modem or data set.
Data Carrier Detect. An active low indicates the modem or data
set has detected a data carrier.
Data Set Ready. An active low indicates the modem or data set
is ready to establish a communication link and transfer data to
the UART.
Clear To Send. It is the modem control input.
The function of these pins can be tested by reading Bit 4 of the
handshake status register.
UART A Data Terminal Ready. An active low informs the
modem or data set that the controller is ready to communicate.
During power-on reset, this pin is pulled down internally and is
defined as PHEFRAS, which provides the power-on value for
CR16 bit 0 (HEFRAS). While it is at Low, it selects the EFER
(Extended Functions Enable Register) to be 250H. While it is at
High, it selects the EFER to be 3F0H. A 4.7 kΩ is recommended
when intends to pull up at power-on reset.
UART A Request To Send. An active low informs the modem or
data set that the controller is ready to send data.
During power-on reset, this pin is pulled up internally and is
defined as PPNPCVS, which provides the power-on value for
CR16 bit 2 (PNPCVS). While it is at Low, all PnP-related
registers (CR20 to CR29) are all set to be 0s. While it is at High,
all PnP-related registers (CR20 to CR 29) are set to default
values. A 4.7 kΩ is recommended when intends to pull down at
power-on reset.
UART A Serial Output. It is used to transmit serial data out to the
communication link.
During power-on reset, this pin is pulled up internally and used to
enable or disable the FDC. While it is at Low, FDC PnP-related
register (CR20) is set to be 0, i.e. FDC is disabled. While it is at
High, CR20 is set to the default value, i.e. FDC is enabled. A
4.7 kΩ is recommended when intends to pull down at power-on
reset.
Publication Release Date: March 1998
-7-
Version 0.61