W83877TF Datasheet, PDF (3/154 Pages) Winbond – I/O chip disk drive adapter

W83877TF
3.2 Register Address
TABLE 3-1 UART Register Bit Map
Register Address Base
8
BDLAB = 0
Receiver
Buffer
Register
(Read Only)
8
Transmitter
BDLAB = 0 ^{Buffer Register}
(Write Only)
9
Interrupt Control
BDLAB = 0
Register
RBR
TBR
ICR
A
Interrupt Status ISR
Register
(Read Only)
0
RX Data
Bit 0
TX Data
Bit 0
RBR Data
Ready
Interrupt
Enable
(ERDRI)
"0" if
Interrupt
Pending
1
RX Data
Bit 1
TX Data
Bit 1
TBR
Empty
Interrupt
Enable
(ETBREI)
Interrupt
Status
Bit (0)
Bit Number
2
3
RX Data RX Data
Bit 2
Bit 3
4
RX Data
Bit 4
TX Data
Bit 2
USR
Interrupt
Enable
(EUSRI)
Interrupt
Status
Bit (1)
TX Data
Bit 3
HSR
Interrupt
Enable
(EHSRI)
Interrupt
Status
Bit (2)**
TX Data
Bit 4
0
0
A
UART FIFO UFR
FIFO
RCVR
XMIT
DMA
Reserved
Control
Enable
FIFO
FIFO
Mode
Register
Reset
Reset
Select
(Write Only)
B
UART Control UCR
Data
Data
Multiple
Parity
Even
Register
Length
Length
Stop Bits
Bit
Parity
Select
Select
Enable
Enable
Enable
Bit 0
(DLS0)
Bit 1
(DLS1)
(MSBE)
(PBE)
(EPE)
C
Handshake HCR
Data
Request Loopback
IRQ
Internal
Control
Terminal
to
RI
Enable
Loopback
Register
Ready
Send
Input
Enable
(DTR)
(RTS)
D
UART Status USR RBR Data Overrun
Parity Bit
No Stop
Silent
Register
Ready
Error
Error
Bit
Byte
(RDR)
(OER)
(PBER)
Error
(NSER)
Detected
(SBD)
E
Handshake HSR
CTS
DSR
RI Falling
DCD
Clear
Status Register
Toggling Toggling
Edge
Toggling
to Send
(TCTS)
(TDSR)
(FERI)
(TDCD)
(CTS)
F
User Defined UDR
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Register
8
Baudrate Divisor BLL
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
BDLAB = 1 ^{Latch Low}
9
Baudrate
BHL
Bit 8
BDLAB = 1 ^{Divisor Latch}
High
Bit 9
Bit 10
Bit 11
Bit 12
*: Bit 0 is the least significant bit. The least significant bit is the first bit serially transmitted or received.
**: These bits are always 0 in 16450 mode.
5
RX Data
Bit 5
TX Data
Bit 5
0
0
Reversed
Parity
Bit Fixed
Enable
PBFE)
0
TBR
Empty
(TBRE)
Data Set
Ready
(DSR)
Bit 5
Bit 5
Bit 13
6
RX Data
Bit 6
7
RX Data
Bit 7
TX Data
Bit 6
0
TX Data
Bit 7
0
FIFOs
FIFOs
Enabled
Enabled
**
**
RX
Interrupt
Active Level
(LSB)
RX
Interrupt
Active Level
(MSB)
Set
Silence
Enable
(SSE)
Baud rate
Divisor
Latch
Access Bit
(BDLAB)
0
0
TSR
Empty
(TSRE)
Ring
Indicator
(RI)
Bit 6
RX FIFO
Error
Indication
(RFEI) **
Data Carrier
Detect
(DCD)
Bit 7
Bit 6
Bit 7
Bit 14
Bit 15
- 40 -
Publication Release Date: March 1998
Version 0.61