W83877TF Datasheet, PDF (26/154 Pages) Winbond – I/O chip disk drive adapter

W83877TF
2.0 FDC FUNCTIONAL DESCRIPTION
2.1 W83877TF FDC
The floppy disk controller of the W83877TF integrates all of the logic required for floppy disk control.
The FDC implements a PC/AT or PS/2 solution. All programmable options default to compatible
values. The FIFO provides better system performance in multi-master systems. The digital data
separator supports up to data rate 1 M bits/sec. (2 M bits/sec for fast tape drive)
The FDC includes the following blocks: AT interface, Precompensation, Data Rate Selection, Digital
Data Separator, FIFO, and FDC Core.
2.1.1 AT interface
The interface consists of the standard asynchronous signals: RD , WR , A0-A3, IRQ, DMA control,
and a data bus. The address lines select between the configuration registers, the FIFO and
control/status registers. This interface can be switched between PC/AT, Model 30, or PS/2 normal
modes. The PS/2 register sets are a superset of the registers found in a PC/AT.
2.1.2 FIFO (Data)
The FIFO is 16 bytes in size and has programmable threshold values. All command parameter
information and disk data transfers go through the FIFO. Data transfers are governed by the RQM
and DIO bits in the Main Status Register.
The FIFO defaults to disabled mode after any form of reset. This maintains PC/AT hardware
compatibility. The default values can be changed through the CONFIGURE command. The
advantage of the FIFO is that it allows the system a larger DMA latency without causing disk errors.
The following tables give several examples of the delays with a FIFO. The data are based upon the
following formula:
THRESHOLD × (1/Data Rate) *8 - 1.5 µS = DELAY
FIFO THRESHOLD
MAXIMUM DELAY TO SERVICING AT 500K BPS
Data Rate
1 Byte
2 Byte
8 Byte
15 Byte
1 × 16 µS - 1.5 µS = 14.5 µS
2 × 16 µS - 1.5 µS = 30.5 µS
8 × 16 µS - 1.5 µS = 6.5 µS
15 × 16 µS - 1.5 µS = 238.5 µS
FIFO THRESHOLD
MAXIMUM DELAY TO SERVICING AT 1M BPS
Data Rate
1 Byte
2 Byte
8 Byte
15 Byte
1 × 8 µS - 1.5 µS = 6.5 µS
2 × 8 µS - 1.5 µS = 14.5 µS
8 × 8 µS - 1.5 µS = 62.5 µS
15 × 8 µS - 1.5 µS = 118.5 µS
At the start of a command the FIFO is always disabled and command parameters must be sent based
upon the RQM and DIO bit settings in the main status register. When the FDC enters the command
execution phase, it clears the FIFO of any data to ensure that invalid data are not transferred.
- 16 -
Publication Release Date: March 1998
Version 0.61