W83877TF Datasheet, PDF (112/154 Pages) Winbond – I/O chip disk drive adapter

W83877TF
8.2.20 Configuration Register 14 (CR14), default = 00H
When the device is in Extended Function mode and EFIR is 14H, the CR14 register can be accessed
through EFDR. The bit definitions are as follows:
765
43
21
0
GDA0IPI
GDA0OPI
GCS0IOW
GCS0IOR
GIO0CSH
GIOP0MD0
GIOP0MD1
GIOP0MD2
GIOP0MD2-GIOP0MD0 (Bit 7-bit 5): GIOP0 pin mode selection
GIOP0MD2
0
0
0
0
1
GIOP0MD1
0
0
1
1
X
GIOP0MD0
0
1
0
1
X
GIOP0 pin
inactive (tri-state)
as a data output pin (SD0→GIOP0), when (AEN = L)
AND (NIOW = L) AND (SA10-0 = GIO0AD10-0), the
value of SD0 will be present on GIOP0
as a data input pin (GIOP0→SD0), when (AEN = L)
AND (NIOR = L) AND (SA10-0 = GIO0AD10-0), the
value of GIOP0 will be present on SD0
as a data input/output pin (GIOP0↔SD0).
When (AEN = L) AND (NIOW = L) AND (SA10-0 =
GIO0AD10-0), the value of SD0 will be present on
GIOP0 When (AEN = L) AND (NIOR = L) AND (SA10-
0 = GIO0AD10-0), the value of GIOP0 will be present
on SD0
as a Chip Select pin, the pin will be active at (AEN =
L) AND (SA10-0 = GIO0AD10-0) OR (NIOR = L) OR
(NIOW = L)
GIO0CSH(Bit 4):
0
the Chip Select pin will be active LOW when (AEN = L) AND (SA10-0 = GIO0AD10-
0) OR (NIOR = L) OR (NIOW = L)
1
the Chip Select pin will be active HIGH when (AEN = L) AND (SA10-0 = GIO0AD10-
0) OR (NIOR = L) OR (NIOW = L)
GCS0IOR (Bit 3): See below.
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Publication Release Date: March 1998
Version 0.61