W83877TF Datasheet, PDF (130/154 Pages) Winbond – I/O chip disk drive adapter

W83877TF
GPEAD7 - GPEAD1 (Bit7 - bit 1): Base address of the power management register block GPE.
This address is the base address of GPE0_BLK in the ACPI specification. The based address should
range from 01,0000,0000_b to 11,1111,1000_b ,i.e., 100H ~ 3F8H, where bit 0 of the base address
should be set to 0 and the based address is in the 8-byte alignment. Note that the base address of
GPE1_BLK is GPE0_BLK + 4.
Bit 0: Reserved, fixed at 0.
8.2.40 Configuration Register 35 (CR35), default=00H
When the device is in Extended Function mode and EFIR is 35H, the CR35 register can be accessed
through EFDR. The bit definitions are as follows:
765
43
21
0
URACNT0
URACNT1
URACNT2
URACNT3
URACNT4
URACNT5
URACNT6
URACNT7
URACNT7 - URACNT0 (Bit 7 - bit 0): UART A idle timer count.
This register is used to specify the initial value of UART A idle timer. Once UART A enters the
working state (that is, after any access to this device, any IRQ, and any external input), the power
down machine of UART A reloads this count value and the idle timer counts down. When the timer
counts down to zero, UART A enters the power down state ,i.e., sleeping state. If this register is set to
00H, the power down function will be invalid. The time resolution of this value is minute or second,
which is defined by the TMIN_SEL bit of the CR3A. Note that (1). this register is valid only when the
power management function of UART A is enabled, that is, CHIPPME=1 (CR32 bit 7) and
URAPME=1 (CR32 bit 1), (2). If the register is set to 00H, UART A will remain in the current
state(working or sleeping).
8.2.41 Configuration Register 36 (CR36), default=00H
When the device is in Extended Function mode and EFIR is 36H, the CR36 register can be accessed
through EFDR. The bit definitions are as follows:
765
43
21
0
URBCNT0
URBCNT1
URBCNT2
URBCNT3
URBCNT4
URBCNT5
URBCNT6
URBCNT7
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Publication Release Date: March 1998
Version 0.61