TA1360AFG_05 Datasheet, PDF (97/110 Pages) Toshiba Semiconductor – YCbCr/YPbPr Signal and Sync Processor for Digital TV, Progressive Scan TV and Double Scan TV

TA1360AFG
Note Characteristics
HA03 Polarity detection
range
Test Conditions
1. Set subaddress (00) data to 40H.
2. Input signal B (as shown in the figure below) to TP50 pin.
3. Decrease signal B duty from 10% (to shorter negative polarity period) and measure signal B
duty (HD_DUTY1) when #50 input signal phase no longer locks with that of #37 (H-OUT).
4. Increase signal B duty from 10% (to longer negative polarity period) and measure signal B duty
(HD_DUTY2) when #39 (FBP input) phase changes in relation to signal B.
5. Further increase signal B duty (to longer negative polarity period) and measure signal B duty
(HD_DUTY3) when #50 input signal phase no longer locks with that of #37 (H-OUT).
6. Decrease signal B duty from 90 % (to shorter negative polarity period) and measure signal B
duty (HD_DUTY4) when #39 (FBP input) phase changes in relation to signal B.
31.75 µs
Signal B
A
1.5 V
B
Duty = A/B × 100% (0 to 100%)
HA04 Sync input threshold 1. Set subaddress (00) data to 82H, and TEST mode to 01.
amplitude
2. Connect variable power supply to #53 via 20-kΩ resistor.
3. Set variable power supply voltage to 0 V, and measure #53 voltage. (SYNC_TIP_00) Also
check that #34 voltage is set to Low (GND level).
4. Increase variable power supply voltage so that #34 voltage becomes High (VCC level).
Measure #53 voltage. (SYNC_OFF_00)
5. Calculate the following equation to determine SYNC input separation level at SYNC separation
level is 00. V_thS00 = (SYNC_OFF_00 − SYNC_TIP_00)/0.286 × 100
6. Change SYNC separation level to 01, 10, and 11. Calculate following equations to determine
VthS01, VthS10, and VthS11.
V_thS01 = (SYNC_OFF_01 − SYNC_TIP_01)/0.286 × 100
V_thS10 = (SYNC_OFF_10 − SYNC_TIP_10)/0.286 × 100
V_thS11 = (SYNC_OFF_11 − SYNC_TIP_11)/0.286 × 100
＃53
1H
40IRE
(= 286 mVp-p)
＃34
(SYNC output mode）
0.08H
Sync separation level
Sync tip level
97
2005-08-18