TA1360AFG_05 Datasheet, PDF (42/110 Pages) Toshiba Semiconductor – YCbCr/YPbPr Signal and Sync Processor for Digital TV, Progressive Scan TV and Double Scan TV

TA1360AFG
Characteristics
Symbol
Test
Circuit
Test Condition
Min Typ. Max Unit
Vertical black peak detection
pulse
Vertical blanking end phase
VP output voltage
000
001
010
011
100
101
110
High
Low
VBPP_0E
VBPP_0S
VBPP_1E
VBPP_1S
VBPP_2E
VBPP_2S
VBPP_3E
VBPP_3S
VBPP_4E
VBPP_4S
VBPP_5E
VBPP_5S
VBPP_6E
VBPP_6S
V_BLKMIN
V_BLKMAX
V_VPH
V_VPL
15.75 kHz
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
pin 35 voltage
⎯
⎯
51
52
53
1099.5 1100.5 1101.5
51
52
53
729.5 730.5 731.5
49.5 50.5 51.5
599.5 600.5 601.5
(Note V03) 49.5 50.5 51.5
H
544.5 545.5 546.5
51
52
53
499.5 500.5 501.5
51
52
53
289.5 290.5 291.5
51
52
53
239.5 240.5 241.5
15
16
17
(Note V04)
H
45
46
47
4.6 5.0 5.4
V
⎯
0.1
0.5
10.0 11.6 13.4
28.125 kHz ⎯
5.4 6.4 8.8
31.5 kHz
⎯
4.8 5.8 7.6
SYNC input to VP output delay time
⎯
µs
33.75 kHz ⎯
4.4 5.4 7.2
37.9 kHz
⎯
3.9 4.8 6.6
45 kHz
⎯
3.1 4.1 5.9
Compression BLK 1
(start phase)
CBLK1_000min ⎯
000
CBLK1_000max ⎯
CBLK1_001min ⎯
001
CBLK1_001max ⎯
CBLK1_010min ⎯
010
CBLK1_010max ⎯
CBLK1_011min ⎯
011
CBLK1_011max ⎯
CBLK1_100min ⎯
100
CBLK1_100max ⎯
CBLK1_101min ⎯
101
CBLK1_101max ⎯
CBLK1_110min ⎯
110
CBLK1_110max ⎯
1087 1088 1089
1117 1118 1119
719 720 721
749 750 751
591 592 593
621 622 623
527 528 529
⎯
H
557 558 559
487 488 489
517 518 519
279 280 281
309 310 311
223 224 225
253 254 255
42
2005-08-18