TA1360AFG_05 Datasheet, PDF (25/110 Pages) Toshiba Semiconductor – YCbCr/YPbPr Signal and Sync Processor for Digital TV, Progressive Scan TV and Double Scan TV

TA1360AFG
Note 4: Power supply sequence
At power-on, power should be supplied to the power supply pins according to the following sequence:
1. Pin 31 (I²L VDD)
2. Pin 45 (DEF/DAC V_CC)
3. Pins 16 and 75 (YC V_CC/RGB V_CC)
Supply power to pin 37 via zener diode through resistor from pin 45. (See “Application Circuit”.)
BUS preset value is become undefined and caused malfunction of the IC unless supplying power to all
supply pins or follow the power supply sequence described above. When the frequency of horizontal output
(pin 37) became undefined, horizontal transistor may be damaged. When the TA1360F is used for CRT,
control horizontal oscillation frequency by pins 41 and 55.
V
DEF/DAC V_CC
Horizontal output 6.0 V (typ.)
POR release voltage (BUS operation) 4.6 V (typ.)
Logic operation 1.3 V (typ.)
I²L V_DD
Figure B
t
Timing chart that indicates the timing from power-on
till horizontal output. (At Ta = 25 C°)
25
2005-08-18