TA1360AFG_05 Datasheet, PDF (14/110 Pages) Toshiba Semiconductor – YCbCr/YPbPr Signal and Sync Processor for Digital TV, Progressive Scan TV and Double Scan TV

TA1360AFG
Bus Control Features
Write Mode
Resister Name
Description
Preset Value
H-FREQ1/2
Switches horizontal oscillation frequency. (See the appendix 1)
33.75 kHz
Switches horizontal output duty.
H-DUTY
41%
0: 41% 1: 47%
YUV-SW
Switches YUV input.
0: INPUT-1 (Y1/C_b1/C_r1) 1: INPUT-2 (Y2/C_b2/C_r2)
Switches DAC controlling output.
INPUT-1
DAC 1
0: OPEN (high) 1: ON (low)
Controls 1-bit DAC of open-collector when TEST is 00.
OPEN
Outputs H/C-SYNC from pin 34 when TEST is 01.
Switches DAC controlling output.
0: ON (low), 1: OPEN (high)
DAC 2
ON
Controls 1-bit DAC of open-collector when TEST is 00.
Outputs ACB reference pulse from pin 23 when TEST is 01.
SYNC-SW
Switches sync input.
0: Selects HD/VD input. 1: Selects SYNC input.
HD/VD
Adjusts horizontal picture position (phase).
HORIZONTAL POSITION 0000000: −12.5% 1111111: +12.5%
CENTER
Note: VP output width (pin 35) varies with a change of horizontal position.
Switches clamp pulse phase.
0: 0.7-µs (2.5%) width, 1.1-µs (3.8%) delay from HD stop phase.
CLP-PHS
1: 0.7-µs (2.4%) width, 0.2-µs (0.7%) delay from HD stop phase
when no signal, 0.8-µs (2.7%) width that is 1.2-µs (4.2%) delay from FBP start
phase.
1.1-µs delay
Also switches CP phase of CP-OUT (pin 47).
ACB MODE
Sets ACB mode; Sets converged reference level.
00: ACB OFF (cutoff BUS control), 01: ACB ON (5 IRE),
10: ACB ON (10 IRE) 11: ACB ON (20 IRE)
ACB ON
(10 IRE)
SCP-SW
SCP (sand castle pulse) Switches modes.
0: Internal Mode 1: External input Mode
Internal Mode
Switches phase of black-stretch-detection stop pulse.
HBP-PHS1 = 0 and HBP-PHS2 = 0: FBP ± 3%
HBP-PHS1 = 0 and HBP-PHS2 = 1: FBP ± 8%
HBP-PHS1/2
HBP-PHS1 = 1 and HBP-PHS2 = 0: FBP ± 13%
±3%
HBP-PHS1 = 1 and HBP-PHS2 = 1: FBP ± 18%
Leaving Y open and setting the test circuit SW70 to C enable to monitor H/V-BPP
(black-stretch-detection stop pulse) width through pin 70.
Switches Sync SEP-level.
SYNC SEP-LEVEL
16%
00: 16% 01: 24% 10: 32% 11: 40% (At 1125I/60)
Test Mode:
TEST
Controls 1-bit DAC of open-collector when TEST is 00.
Outputs H/C-SYNC from pin 34, and ACB reference pulse from pin 23 when TEST ⁰⁰
is 01.
Do not set TEST to 10/11 for that is shipment TEST Mode.
14
2005-08-18