TA1360AFG_05 Datasheet, PDF (91/110 Pages) Toshiba Semiconductor – YCbCr/YPbPr Signal and Sync Processor for Digital TV, Progressive Scan TV and Double Scan TV

TA1360AFG
Note
No.
Characteristics
Test Conditions
SW Mode
SW68 SW67 SW66 SW26 SW25 SW24 SW21 SW19 SW18
Test Method
T34 OSD ACL
A
B
B
A
A
A
A
A
B 1. Input signal 1(f₀ = 100 kHz, picture period amplitude = 0.2 Vp-p) from pin 68. Control drive
characteristic
gain adjustment data so that pins 14 and 13 picture period amplitude equals that of pin 12.
2. Set subaddress (07) data to (01).
3. Apply 5-V external voltage to pins 1 and 80.
4. Input signal 1 (f₀ = 100 kHz, picture period amplitude = 0.2 Vp-p) from pin 18.
5. Measure pin 12 picture period amplitude, vOSDACL1.
6. Apply “pin 78 DC voltage − 0.8 V” to pin 78 from external power supply, and measure pin
12-picture period amplitude, vOSDACL2.
7. Apply “pin 78 DC voltage − 1.3 V” to pin 78 from external power supply, and measure pin
12-picture period amplitude, vOSDACL3.
8. OSDACL₁ = −20 × log (vOSDACL2/vOSDACL1)
OSDACL₂ = −20 × log (vOSDACL3/vOSDACL1)
9. OSDACL3、OSDACL4 Change subaddress (07) data to (80), and repeat the steps 6 to 8
above to measure OSDACL3 and OSDACL4.
91
2005-08-18