TA1360AFG_05 Datasheet, PDF (23/110 Pages) Toshiba Semiconductor – YCbCr/YPbPr Signal and Sync Processor for Digital TV, Progressive Scan TV and Double Scan TV

Data Transmit Format 1
TA1360AFG
S Slave address 0 A
7 bit
Sub address
8 bit
MSB
S: Start condition
MSB
A: Acknowledgement
A Transmit data A P
9 bit
MSB
P: Stop condition
Data Transmit Format 2
S Slave address 0 A Sub address A Transmit data 1 A ･･････
･･････ Sub address A Transmit data n A P
Data Receive Format
S Slave address
7 bit
MSB
1A
Receive data
8 bit
MSB
AP
To receive data, the master transmitter changes to a receiver immediately after the first acknowledgement. The
slave receiver changes to a transmitter.
The stop condition is always created by the master.
Optional Data Transmit Format
S Slave address
7 bit
MSB
0A1
Sub address
7 bit
MSB
A Transmit data 1
8 bit
MSB
････ Transmit data n
8 bit
MSB
AP
In this way, sub addresses are automatically incremented from the specified sub address and data are set.
I²C BUS Conditions
Characteristics
Low level input voltage
High level input voltage
Low level output voltage at 3 mA sink current
Input current each I/O pin with an input voltage
between 0.1 VDD and 0.9 VDD
Capacitance for each I/O pin
SCL clock frequency
Hold time START condition
Low period of SCL clock
High period of SCL clock
Set-up time for a repeated START condition
Data hold time
Data set-up time
Set-up time for STOP condition
Bus free time between a STOP and START condition
Symbol
V_IL
V_IH
V_OL1
I_i
C_i
f_SCL
t_HD;STA
t_LOW
t_HIGH
t_SU;STA
t_HD;DAT
t_SU;DAT
t_SU;STO
t_BUF
Min Typ. Max Unit
0
⎯
1.0
V
1.8
⎯
Vcc
V
0
⎯
0.4
V
−10 ⎯
10
µA
⎯
⎯
10
pF
0
⎯ 100 kHz
4.0
⎯
⎯
µs
4.7
⎯
⎯
µs
4.0
⎯
⎯
µs
4.7
⎯
⎯
µs
350 ⎯
⎯
ns
250 ⎯
⎯
ns
4.0
⎯
⎯
µs
4.7
⎯
⎯
µs
23
2005-08-18