LM3S5P36 Datasheet, PDF (833/1050 Pages) Texas Instruments – Stellaris® LM3S5P36 Microcontroller

Stellaris^® LM3S5P36 Microcontroller
Register 53: USB Transmit Control and Status Endpoint 1 Low (USBTXCSRL1),
offset 0x112
Register 54: USB Transmit Control and Status Endpoint 2 Low (USBTXCSRL2),
offset 0x122
Register 55: USB Transmit Control and Status Endpoint 3 Low (USBTXCSRL3),
offset 0x132
Register 56: USB Transmit Control and Status Endpoint 4 Low (USBTXCSRL4),
offset 0x142
Register 57: USB Transmit Control and Status Endpoint 5 Low (USBTXCSRL5),
offset 0x152
Register 58: USB Transmit Control and Status Endpoint 6 Low (USBTXCSRL6),
offset 0x162
Register 59: USB Transmit Control and Status Endpoint 7 Low (USBTXCSRL7),
offset 0x172
Register 60: USB Transmit Control and Status Endpoint 8 Low (USBTXCSRL8),
offset 0x182
Register 61: USB Transmit Control and Status Endpoint 9 Low (USBTXCSRL9),
offset 0x192
Register 62: USB Transmit Control and Status Endpoint 10 Low
(USBTXCSRL10), offset 0x1A2
Register 63: USB Transmit Control and Status Endpoint 11 Low
(USBTXCSRL11), offset 0x1B2
Register 64: USB Transmit Control and Status Endpoint 12 Low
(USBTXCSRL12), offset 0x1C2
Register 65: USB Transmit Control and Status Endpoint 13 Low
(USBTXCSRL13), offset 0x1D2
Register 66: USB Transmit Control and Status Endpoint 14 Low
(USBTXCSRL14), offset 0x1E2
Register 67: USB Transmit Control and Status Endpoint 15 Low
(USBTXCSRL15), offset 0x1F2
USBTXCSRLn is an 8-bit register that provides control and status bits for transfers through the
currently selected transmit endpoint.
USB Transmit Control and Status Endpoint 1 Low (USBTXCSRL1)
Base 0x4005.0000
Offset 0x112
Type R/W, reset 0x00
7
6
5
4
3
2
1
0
reserved CLRDT STALLED STALL FLUSH UNDRN FIFONE TXRDY
Type RO
Reset
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
January 21, 2012
833
Texas Instruments-Production Data