LM3S5P36 Datasheet, PDF (132/1050 Pages) Texas Instruments – Stellaris® LM3S5P36 Microcontroller

Cortex-M3 Peripherals
Interrupt 0-3 Priority (PRI0)
Base 0xE000.E000
Offset 0x400
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
INTD
reserved
INTC
reserved
Type R/W
R/W
R/W
RO
RO
RO
RO
RO
R/W
R/W
R/W
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
INTB
reserved
INTA
reserved
Type R/W
R/W
R/W
RO
RO
RO
RO
RO
R/W
R/W
R/W
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:29
28:24
23:21
20:16
15:13
12:8
7:5
4:0
Name
INTD
reserved
INTC
reserved
INTB
reserved
INTA
reserved
Type
R/W
RO
R/W
RO
R/W
RO
R/W
RO
Reset
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Description
Interrupt Priority for Interrupt [4n+3]
This field holds a priority value, 0-7, for the interrupt with the number
[4n+3], where n is the number of the Interrupt Priority register (n=0 for
PRI0, and so on). The lower the value, the greater the priority of the
corresponding interrupt.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Interrupt Priority for Interrupt [4n+2]
This field holds a priority value, 0-7, for the interrupt with the number
[4n+2], where n is the number of the Interrupt Priority register (n=0 for
PRI0, and so on). The lower the value, the greater the priority of the
corresponding interrupt.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Interrupt Priority for Interrupt [4n+1]
This field holds a priority value, 0-7, for the interrupt with the number
[4n+1], where n is the number of the Interrupt Priority register (n=0 for
PRI0, and so on). The lower the value, the greater the priority of the
corresponding interrupt.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Interrupt Priority for Interrupt [4n]
This field holds a priority value, 0-7, for the interrupt with the number
[4n], where n is the number of the Interrupt Priority register (n=0 for
PRI0, and so on). The lower the value, the greater the priority of the
corresponding interrupt.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
132
January 21, 2012
Texas Instruments-Production Data