LM3S5P36 Datasheet, PDF (412/1050 Pages) Texas Instruments – Stellaris® LM3S5P36 Microcontroller

General-Purpose Input/Outputs (GPIOs)
Table 9-3. GPIO Pad Configuration Examples (continued)
Configuration
GPIO Register Bit Value^a
AFSEL DIR
ODR
DEN
PUR
Digital Input (QEI)
1
X
0
1
?
Digital Output (PWM)
1
X
0
1
?
Digital Output (Timer
1
X
0
1
?
PWM)
Digital Input/Output
1
X
0
1
?
(SSI)
Digital Input/Output
1
X
0
1
?
(UART)
Analog Input
(Comparator)
0
0
0
0
0
Digital Output
(Comparator)
1
X
0
1
?
a. X=Ignored (don’t care bit)
?=Can be either 0 or 1, depending on the configuration
PDR
?
?
?
?
?
0
?
DR2R
X
?
?
?
?
X
?
DR4R
X
?
?
?
?
X
?
DR8R
X
?
?
?
?
X
?
SLR
X
?
?
?
?
X
?
Table 9-4. GPIO Interrupt Configuration Example
Register
Desired Interrupt
Event Trigger
Pin 2 Bit Value^a
7
6
GPIOIS
0=edge
1=level
X
X
GPIOIBE
0=single edge
X
X
1=both edges
GPIOIEV
0=Low level, or falling X
X
edge
1=High level, or rising
edge
GPIOIM
0=masked
0
0
1=not masked
a. X=Ignored (don’t care bit)
5
X
X
X
0
4
X
X
X
0
3
X
X
X
0
2
0
0
1
1
1
X
X
X
0
0
X
X
X
0
9.4 Register Map
Table 9-6 on page 413 lists the GPIO registers. Each GPIO port can be accessed through one of
two bus apertures. The legacy aperture, the Advanced Peripheral Bus (APB), is backwards-compatible
with previous Stellaris parts. The other aperture, the Advanced High-Performance Bus (AHB), offers
the same register map but provides better back-to-back access performance than the APB bus.
Important: The GPIO registers in this chapter are duplicated in each GPIO block; however,
depending on the block, all eight bits may not be connected to a GPIO pad. In those
cases, writing to unconnected bits has no effect, and reading unconnected bits returns
no meaningful data.
The offset listed is a hexadecimal increment to the register’s address, relative to that GPIO port’s
base address:
■ GPIO Port A (APB): 0x4000.4000
■ GPIO Port A (AHB): 0x4005.8000
412
January 21, 2012
Texas Instruments-Production Data