LM3S5P36 Datasheet, PDF (7/1050 Pages) Texas Instruments – Stellaris® LM3S5P36 Microcontroller

Stellaris^® LM3S5P36 Microcontroller
12.3.3 Hardware Sample Averaging Circuit ............................................................................. 532
12.3.4 Analog-to-Digital Converter .......................................................................................... 532
12.3.5 Differential Sampling ................................................................................................... 535
12.3.6 Internal Temperature Sensor ........................................................................................ 538
12.3.7 Digital Comparator Unit ............................................................................................... 538
12.4 Initialization and Configuration ..................................................................................... 543
12.4.1 Module Initialization ..................................................................................................... 543
12.4.2 Sample Sequencer Configuration ................................................................................. 544
12.5 Register Map .............................................................................................................. 544
12.6 Register Descriptions .................................................................................................. 546
13 Universal Asynchronous Receivers/Transmitters (UARTs) ............................. 604
13.1 Block Diagram ............................................................................................................ 605
13.2 Signal Description ....................................................................................................... 605
13.3 Functional Description ................................................................................................. 606
13.3.1 Transmit/Receive Logic ............................................................................................... 606
13.3.2 Baud-Rate Generation ................................................................................................. 607
13.3.3 Data Transmission ...................................................................................................... 607
13.3.4 Serial IR (SIR) ............................................................................................................. 608
13.3.5 ISO 7816 Support ....................................................................................................... 609
13.3.6 LIN Support ................................................................................................................ 609
13.3.7 FIFO Operation ........................................................................................................... 611
13.3.8 Interrupts .................................................................................................................... 611
13.3.9 Loopback Operation .................................................................................................... 612
13.3.10 DMA Operation ........................................................................................................... 612
13.4 Initialization and Configuration ..................................................................................... 613
13.5 Register Map .............................................................................................................. 614
13.6 Register Descriptions .................................................................................................. 615
14 Synchronous Serial Interface (SSI) .................................................................... 660
14.1 Block Diagram ............................................................................................................ 661
14.2 Signal Description ....................................................................................................... 661
14.3 Functional Description ................................................................................................. 662
14.3.1 Bit Rate Generation ..................................................................................................... 662
14.3.2 FIFO Operation ........................................................................................................... 662
14.3.3 Interrupts .................................................................................................................... 663
14.3.4 Frame Formats ........................................................................................................... 664
14.3.5 DMA Operation ........................................................................................................... 671
14.4 Initialization and Configuration ..................................................................................... 672
14.5 Register Map .............................................................................................................. 673
14.6 Register Descriptions .................................................................................................. 674
15 Inter-Integrated Circuit (I²C) Interface ................................................................ 702
15.1 Block Diagram ............................................................................................................ 703
15.2 Signal Description ....................................................................................................... 703
15.3 Functional Description ................................................................................................. 703
15.3.1 I²C Bus Functional Overview ........................................................................................ 704
15.3.2 Available Speed Modes ............................................................................................... 706
15.3.3 Interrupts .................................................................................................................... 707
15.3.4 Loopback Operation .................................................................................................... 708
15.3.5 Command Sequence Flow Charts ................................................................................ 708
January 21, 2012
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