LM3S5P36 Datasheet, PDF (531/1050 Pages) Texas Instruments – Stellaris® LM3S5P36 Microcontroller

Stellaris^® LM3S5P36 Microcontroller
position (the PHASE field in the ADCSPC register is 0x0). ADC module 1 can be configured to sample
at 180 (PHASE = 0x8). The two modules can be be synchronized using the GSYNC and SYNCWAIT
bits in the ADC Processor Sample Sequence Initiate (ADCPSSI) register. Software could then
combine the results from the two modules to create a sample rate of two million samples/second
at 16 MHz as shown in Figure 12-4 on page 531.
Figure 12-4. Doubling the ADC Sample Rate
ADC Sample Clock
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
GSYNC
ADC 0 PHASE 0x0 (0.0°)
ADC 1 PHASE 0x8 (180.0°)
Using the ADCSPC register, ADC0 and ADC1 may provide a number of interesting applications:
■ Coincident sampling of different signals. The sample sequence steps run coincidently in both
converters.
– ADC Module 0, ADCSPC = 0x0, sampling AIN0
– ADC Module 1, ADCSPC = 0x0, sampling AIN1
■ Skewed sampling of the same signal. The sample sequence steps are 1/2 of an ADC clock (500
µs for a 1Ms/s ADC) out of phase with each other. This configuration doubles the conversion
bandwidth of a single input when software combines the results as shown in Figure
12-5 on page 531.
– ADC Module 0, ADCSPC = 0x0, sampling AIN0
– ADC Module 1, ADCSPC = 0x8, sampling AIN0
Figure 12-5. Skewed Sampling
ADC0 S1 S2 S3 S4 S5 S6 S7 S8
ADC1
S1 S2 S3 S4 S5 S6 S7 S8
January 21, 2012
531
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